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c62cfa2efb
-Add new PMU ops to get NEXT core irq mask -Add support to handle NEXT core interrupt request. Bug 200659053 Bug 3199589 Change-Id: I78738f074a425f8934bbba28bf6996eeec7ab05a Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2457077 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
84 lines
2.4 KiB
C
84 lines
2.4 KiB
C
/*
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* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/pmu/debug.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/io.h>
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#include <nvgpu/hw/gk20a/hw_pwr_gk20a.h>
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#include "pmu_gk20a.h"
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u32 gk20a_pmu_get_irqmask(struct gk20a *g)
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{
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u32 mask = 0U;
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mask = nvgpu_readl(g, pwr_falcon_irqmask_r());
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mask &= nvgpu_readl(g, pwr_falcon_irqdest_r());
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return mask;
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}
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void gk20a_pmu_isr(struct gk20a *g)
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{
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struct nvgpu_pmu *pmu = g->pmu;
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u32 intr = 0U;
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u32 mask = 0U;
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nvgpu_log_fn(g, " ");
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nvgpu_mutex_acquire(&pmu->isr_mutex);
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intr = nvgpu_readl(g, pwr_falcon_irqstat_r());
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mask = g->ops.pmu.get_irqmask(g);
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nvgpu_pmu_dbg(g, "received PMU interrupt: stat:0x%08x mask:0x%08x",
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intr, mask);
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if (!pmu->isr_enabled || ((intr & mask) == 0U)) {
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nvgpu_log_info(g,
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"clearing unhandled interrupt: stat:0x%08x mask:0x%08x",
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intr, mask);
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nvgpu_writel(g, pwr_falcon_irqsclr_r(), intr);
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nvgpu_mutex_release(&pmu->isr_mutex);
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return;
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}
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intr = intr & mask;
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if (g->ops.pmu.handle_ext_irq != NULL) {
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g->ops.pmu.handle_ext_irq(g, intr);
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}
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nvgpu_writel(g, pwr_falcon_irqsclr_r(), intr);
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#ifdef CONFIG_NVGPU_LS_PMU
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if (nvgpu_pmu_get_fw_state(g, pmu) == PMU_FW_STATE_OFF) {
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nvgpu_mutex_release(&pmu->isr_mutex);
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return;
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}
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gk20a_pmu_handle_interrupts(g, intr);
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#endif
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nvgpu_mutex_release(&pmu->isr_mutex);
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}
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