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62d6f753d2
Volta+ chips supports PES floorsweeping and Ampere+(iGPU) chips supports ROP floorsweeping. At present, the driver isn't aware of PES, ROP floorsweeping, make the driver PES, ROP floorsweeping aware by introducing the following fields in nvgpu_gr_config: - gpc_(rop/pes)_mask: Contains the bit mask of non FSed ROP/PES units per GPC. - gpc_(rop/pes)_logical_id_map: Translates per GPC ROP/PES physical id to logical id. Introduce the following HAL functions to read PES/ROP FS data: - gops_fuse.fuse_status_opt_(pes/rop)_gpc: This fuction gets the FS config from the fuse. - gops_top.get_max_(pes/rop)_per_gpc: Gets the maximum number of PES/ROP units that can be present in a GPC. In addition, introduce the enabled flag NVGPU_SUPPORT_PES_FS to identify chips which support PES floorsweeping, piggyback on NVGPU_SUPPORT_ROP_IN_GPC enabled flag to identify ROP floorsweeping. Bug 3524791 Change-Id: I065bab6c02618fe38892c8c890b069c340b85301 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2679570 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
77 lines
2.5 KiB
C
77 lines
2.5 KiB
C
/*
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* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include "top_gv11b.h"
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#include <nvgpu/hw/gv11b/hw_top_gv11b.h>
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u32 gv11b_top_get_num_lce(struct gk20a *g)
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{
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u32 reg_val, num_lce;
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reg_val = nvgpu_readl(g, top_num_ces_r());
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num_lce = top_num_ces_value_v(reg_val);
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nvgpu_log_info(g, "num LCE: %d", num_lce);
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return num_lce;
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}
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u32 gv11b_top_get_max_pes_per_gpc(struct gk20a *g)
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{
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u32 tmp;
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tmp = nvgpu_readl(g, top_num_pes_per_gpc_r());
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return top_num_pes_per_gpc_value_v(tmp);
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}
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int gv11b_device_info_parse_data(struct gk20a *g, u32 table_entry, u32 *inst_id,
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u32 *pri_base, u32 *fault_id)
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{
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if (top_device_info_data_type_v(table_entry) !=
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top_device_info_data_type_enum2_v()) {
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nvgpu_err(g, "Unknown device_info_data_type %u",
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top_device_info_data_type_v(table_entry));
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return -EINVAL;
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}
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nvgpu_log_info(g, "Entry_data to be parsed 0x%x", table_entry);
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*pri_base = (top_device_info_data_pri_base_v(table_entry) <<
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top_device_info_data_pri_base_align_v());
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nvgpu_log_info(g, "Pri Base addr: 0x%x", *pri_base);
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if (top_device_info_data_fault_id_v(table_entry) ==
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top_device_info_data_fault_id_valid_v()) {
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*fault_id = top_device_info_data_fault_id_enum_v(table_entry);
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} else {
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*fault_id = U32_MAX;
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}
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nvgpu_log_info(g, "Fault_id: %u", *fault_id);
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*inst_id = top_device_info_data_inst_id_v(table_entry);
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nvgpu_log_info(g, "Inst_id: %u", *inst_id);
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return 0;
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}
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