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ae2d561c48
- Add support for taking static PG config values from DT nodes - Check those values against valid set of values for GPC, TPC and FBP - Store valid values in g->gpc_pg_mask, g->fbp_pg_mask and g->tpc_pg_mask[] array. Bug 200768322 JIRA NVGPU-6433 Change-Id: Ifc87e7d369034b1daa13866bc16a970602514bf6 Signed-off-by: Divya <dsinghatwari@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2594802 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
125 lines
3.8 KiB
C
125 lines
3.8 KiB
C
/*
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* GV11B TPC
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*
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* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include "tpc_gv11b.h"
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#ifdef CONFIG_NVGPU_STATIC_POWERGATE
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/*
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* validate the requested tpc pg mask
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* with respect to the current hw value.
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*/
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int gv11b_tpc_pg(struct gk20a *g, bool *can_tpc_pg)
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{
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int err = 0;
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u32 fuse_status = 0x0;
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if (g->ops.fuse.fuse_status_opt_tpc_gpc != NULL) {
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fuse_status = g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0);
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}
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if (fuse_status == 0x0) {
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/*
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* fuse_status = 0x0 means all TPCs are active
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* thus, tpc_pg_mask passed by user or DT
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* can be applied to powergate the TPC(s).
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*/
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*can_tpc_pg = true;
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} else {
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/* if hardware has already floorswept any TPC
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* (fuse_status != 0x0) and if TPC PG mask
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* sent from userspace/DT node is 0x0 (it is trying to
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* set all TPCs active), GPU will be powered on
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* with the default HW fuse_status setting. It cannot
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* un-floorsweep any TPC.
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* thus, set g->tpc_pg_mask to fuse_status value
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* and boot with default HW fuse settings.
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*/
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if (g->tpc_pg_mask[PG_GPC0] == 0x0U) {
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*can_tpc_pg = true;
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g->tpc_pg_mask[PG_GPC0] = fuse_status;
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} else if (fuse_status == g->tpc_pg_mask[PG_GPC0]) {
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*can_tpc_pg = true;
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} else if ((fuse_status & g->tpc_pg_mask[PG_GPC0]) ==
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fuse_status) {
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/*
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* if HW has already floorswept any TPC
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* check if the tpc_pg_mask sent by user
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* is floorsweeping only additional TPCs
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*/
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*can_tpc_pg = true;
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} else {
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/* If userspace sends a TPC PG mask such that
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* it tries to un-floorsweep any TPC which is
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* already powergated from hardware, then
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* such mask is invalid.
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* In this case set tpc pg mask to 0x0
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* Return -EINVAL here and halt GPU poweron.
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*/
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nvgpu_err(g, "Invalid TPC_PG mask: 0x%x",
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g->tpc_pg_mask[PG_GPC0]);
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*can_tpc_pg = false;
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g->tpc_pg_mask[PG_GPC0] = 0x0;
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err = -EINVAL;
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}
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}
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return err;
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}
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/* To-do: check to rename this function */
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void gv11b_gr_pg_tpc(struct gk20a *g)
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{
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u32 tpc_pg_status = g->ops.fuse.fuse_status_opt_tpc_gpc(g, PG_GPC0);
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/*
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* if the fuse status for tpc is same as tpc_pg_mask
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* passed, then do nothing and return
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*/
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if (tpc_pg_status == g->tpc_pg_mask[PG_GPC0]) {
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return;
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}
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/*
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* write to fuse_ctrl register to update the fuse settings
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* as per the tpc_pg_mask
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*/
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g->ops.fuse.fuse_ctrl_opt_tpc_gpc(g, PG_GPC0,
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g->tpc_pg_mask[PG_GPC0]);
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/*
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* To confirm that the write was successful
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* read the fuse_status register.
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* The write done is previous step may take some time to
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* get update in fuse_status register
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*/
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do {
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tpc_pg_status = g->ops.fuse.fuse_status_opt_tpc_gpc(g, PG_GPC0);
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} while (tpc_pg_status != g->tpc_pg_mask[PG_GPC0]);
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return;
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}
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#endif
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