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58018f0c1b
Add gk20a_channel_put() pair for gk20a_get_channel_from_file() that now returns the channel with a reference. Also fix resource leaks in gv11b_tsg_ioctl_bind_channel_ex's error paths. Change-Id: Ib348219defa67163657ca534826f504ebc59497e Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1553276 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
96 lines
2.3 KiB
C
96 lines
2.3 KiB
C
/*
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* GV11B TSG IOCTL Handler
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*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/types.h>
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#include "gk20a/gk20a.h"
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#include "gv11b/fifo_gv11b.h"
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#include "gv11b/subctx_gv11b.h"
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#include "ioctl_tsg_t19x.h"
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static int gv11b_tsg_ioctl_bind_channel_ex(struct gk20a *g,
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struct tsg_gk20a *tsg, struct nvgpu_tsg_bind_channel_ex_args *arg)
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{
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struct gk20a_sched_ctrl *sched = &g->sched_ctrl;
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struct channel_gk20a *ch;
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int err = 0;
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nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid);
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nvgpu_mutex_acquire(&sched->control_lock);
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if (sched->control_locked) {
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err = -EPERM;
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goto mutex_release;
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}
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err = gk20a_busy(g);
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if (err) {
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nvgpu_err(g, "failed to power on gpu");
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goto mutex_release;
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}
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ch = gk20a_get_channel_from_file(arg->channel_fd);
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if (!ch) {
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err = -EINVAL;
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goto idle;
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}
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if (arg->subcontext_id < g->fifo.t19x.max_subctx_count) {
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ch->t19x.subctx_id = arg->subcontext_id;
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} else {
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err = -EINVAL;
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goto ch_put;
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}
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nvgpu_log(g, gpu_dbg_info, "channel id : %d : subctx: %d",
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ch->chid, ch->t19x.subctx_id);
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/* Use runqueue selector 1 for all ASYNC ids */
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if (ch->t19x.subctx_id > CHANNEL_INFO_VEID0)
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ch->t19x.runqueue_sel = 1;
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err = ch->g->ops.fifo.tsg_bind_channel(tsg, ch);
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ch_put:
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gk20a_channel_put(ch);
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idle:
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gk20a_idle(g);
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mutex_release:
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nvgpu_mutex_release(&sched->control_lock);
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return err;
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}
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int t19x_tsg_ioctl_handler(struct gk20a *g, struct tsg_gk20a *tsg,
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unsigned int cmd, u8 *buf)
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{
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int err = 0;
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nvgpu_log(g, gpu_dbg_fn, "t19x_tsg_ioctl_handler");
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switch (cmd) {
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case NVGPU_TSG_IOCTL_BIND_CHANNEL_EX:
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{
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err = gv11b_tsg_ioctl_bind_channel_ex(g, tsg,
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(struct nvgpu_tsg_bind_channel_ex_args *)buf);
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break;
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}
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default:
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nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x",
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cmd);
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err = -ENOTTY;
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break;
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}
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return err;
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}
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