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c30afdce02
move fecs_trace polling from kthread to timer API. Jira GVSCI-10883 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Change-Id: I224754b7205f1d0eefdc19a73a98f42e4d3e9d0e Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2700601 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Shashank Singh <shashsingh@nvidia.com> Reviewed-by: Aparna Das <aparnad@nvidia.com> GVS: Gerrit_Virtual_Submit
89 lines
2.4 KiB
C
89 lines
2.4 KiB
C
/*
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* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <nvgpu/bug.h>
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#include <nvgpu/periodic_timer.h>
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#include <linux/async.h>
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static void async_func(void *data, async_cookie_t cookie)
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{
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struct nvgpu_periodic_timer *timer = data;
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timer->fn(timer->arg);
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raw_spin_lock(&timer->lock);
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if (timer->enabled) {
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hrtimer_start(&timer->timer, timer->interval, HRTIMER_MODE_REL);
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}
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raw_spin_unlock(&timer->lock);
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}
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static enum hrtimer_restart timer_callback(struct hrtimer *os_timer)
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{
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struct nvgpu_periodic_timer *timer =
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container_of(os_timer, struct nvgpu_periodic_timer, timer);
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timer->async_cookie = async_schedule(async_func, timer);
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return HRTIMER_NORESTART;
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}
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int nvgpu_periodic_timer_init(struct nvgpu_periodic_timer *timer,
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void (*fn)(void *arg), void *arg)
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{
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hrtimer_init(&timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
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timer->timer.function = timer_callback;
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timer->fn = fn;
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timer->arg = arg;
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timer->interval = ktime_set(0, 0);
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timer->async_cookie = 0;
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timer->enabled = false;
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raw_spin_lock_init(&timer->lock);
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return 0;
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}
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int nvgpu_periodic_timer_start(struct nvgpu_periodic_timer *timer,
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u64 interval_ns)
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{
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raw_spin_lock(&timer->lock);
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timer->interval = ns_to_ktime(interval_ns);
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timer->enabled = true;
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timer->async_cookie = 0;
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hrtimer_start(&timer->timer, timer->interval, HRTIMER_MODE_REL);
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raw_spin_unlock(&timer->lock);
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return 0;
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}
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int nvgpu_periodic_timer_stop(struct nvgpu_periodic_timer *timer)
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{
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raw_spin_lock(&timer->lock);
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if (!timer->enabled) {
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raw_spin_unlock(&timer->lock);
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return 0;
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}
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timer->enabled = false;
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raw_spin_unlock(&timer->lock);
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hrtimer_cancel(&timer->timer);
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if (timer->async_cookie != 0) {
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async_synchronize_cookie(timer->async_cookie + 1);
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}
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return 0;
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}
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int nvgpu_periodic_timer_destroy(struct nvgpu_periodic_timer *timer)
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{
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return nvgpu_periodic_timer_stop(timer);
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}
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