Mahantesh Kumbar 33e9d08610 gpu: nvgpu: Modify dgpu WPR/NON-WPR address space ...

Currently, there is free space of 3MB with current implementation due to
gap between WPR & NON-WPR offset, with this PMU buffers are allocated
between this space & some are after WPR.

So, modified WPR to allocate at 0th offset of bootstrap-region of VIDMEM
& NON-WPR to be at WPR+WPR_SIZE offset of bootstrap-region to make
contiguous free space available till end of bootstrap-region of VIDMEM.

Increased WPR/NON-WPR size from 1MB to 2MB as LS falcon managed
count increased to 4 for Turing & remains 2MB for previous chips too.

Bug 200476497

Change-Id: I92ca5bc9a571330d75a66ce820a1c82442c1f200
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1994653
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2019-01-16 23:24:47 -08:00

..

nvgpu

gpu: nvgpu: Modify dgpu WPR/NON-WPR address space

2019-01-16 23:24:47 -08:00

Makefile

nvgpu: use kernel overlay features

2017-10-29 11:00:55 -07:00