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git://nv-tegra.nvidia.com/linux-nvgpu.git
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ad85b60bb0
Replace the usage of tegra_fuse_readl with nvmem_cell_read_u32 for the below fuse registers added as nvmem cells on v5.10+ kernels. Older nvidia kernels do not have these tegra nvmem cell support. 1. FUSE_GCPLEX_CONFIG_FUSE_0 2. FUSE_RESERVED_CALIB0_0 3. FUSE_PDI0 4. FUSE_PDI1 bug 200633045 Change-Id: I187400720929233fcbc1970c9bbed34347b0a9a7 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2670828 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit
81 lines
2.0 KiB
C
81 lines
2.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2022, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <nvgpu/linux/nvmem.h>
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#include <nvgpu/log.h>
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#include <linux/nvmem-consumer.h>
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#include "os_linux.h"
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#define NVMEM_CELL_GCPLEX_CONFIG_FUSE "gcplex-config-fuse"
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#define NVMEM_CELL_CALIBRATION "calibration"
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#define NVMEM_CELL_PDI0 "pdi0"
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#define NVMEM_CELL_PDI1 "pdi1"
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int nvgpu_tegra_nvmem_read_reserved_calib(struct gk20a *g, u32 *val)
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{
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struct device *dev = dev_from_gk20a(g);
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int ret;
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ret = nvmem_cell_read_u32(dev, NVMEM_CELL_CALIBRATION, val);
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if (ret < 0) {
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nvgpu_err(g, "%s nvmem cell read failed %d",
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NVMEM_CELL_CALIBRATION, ret);
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return ret;
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}
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return 0;
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}
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int nvgpu_tegra_nvmem_read_gcplex_config_fuse(struct gk20a *g, u32 *val)
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{
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struct device *dev = dev_from_gk20a(g);
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int ret;
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ret = nvmem_cell_read_u32(dev, NVMEM_CELL_GCPLEX_CONFIG_FUSE, val);
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if (ret < 0) {
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nvgpu_err(g, "%s nvmem cell read failed %d",
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NVMEM_CELL_GCPLEX_CONFIG_FUSE, ret);
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return ret;
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}
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return 0;
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}
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int nvgpu_tegra_nvmem_read_per_device_identifier(struct gk20a *g, u64 *pdi)
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{
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struct device *dev = dev_from_gk20a(g);
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u32 lo = 0U;
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u32 hi = 0U;
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int err;
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err = nvmem_cell_read_u32(dev, NVMEM_CELL_PDI0, &lo);
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if (err) {
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return err;
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}
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err = nvmem_cell_read_u32(dev, NVMEM_CELL_PDI1, &hi);
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if (err) {
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return err;
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}
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*pdi = ((u64)lo) | (((u64)hi) << 32);
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return 0;
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}
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