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cb110723a5
Add doxygen documentation for private GR structures defined in: gr/gr_config_priv.h gr/gr_falcon_priv.h gr/gr_intr_priv.h gr/gr_priv.h Remove "p_va" field from struct nvgpu_ctxsw_ucode_info since it is unused. Compile out "pm_ctxsw_image_size" with flag CONFIG_NVGPU_DEBUGGER. Compile out "preempt_image_size" with flag CONFIG_NVGPU_GRAPHICS. Replace eUcodeHandshakeInitComplete enum value by macro FALCON_UCODE_HANDSHAKE_INIT_COMPLETE. And remove enum value eUcodeHandshakeMethodFinished since it is unused. Compile "ctxsw_disable_mutex" and "ctxsw_disable_count" in struct nvgpu_gr only if CONFIG_NVGPU_RECOVERY or CONFIG_NVGPU_DEBUGGER is defined Jira NVGPU-4028 Change-Id: Ie8769c1f3f8d313b479b182d3858a6715d49cd4c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2201373 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
134 lines
3.3 KiB
C
134 lines
3.3 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_PRIV_H
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#define NVGPU_GR_PRIV_H
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#include <nvgpu/types.h>
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#include <nvgpu/cond.h>
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struct nvgpu_gr_ctx_desc;
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struct nvgpu_gr_global_ctx_buffer_desc;
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struct nvgpu_gr_obj_ctx_golden_image;
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struct nvgpu_gr_config;
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#ifdef CONFIG_NVGPU_GRAPHICS
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struct nvgpu_gr_zbc;
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struct nvgpu_gr_zcull;
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#endif
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#ifdef CONFIG_NVGPU_DEBUGGER
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struct nvgpu_gr_hwpm_map;
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#endif
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/**
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* GR engine data structure.
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*
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* This is the parent structure to all other GR engine data structures,
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* and holds a pointer to all of them. This structure also stores
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* various fields to track GR engine initialization state.
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*
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* Pointer to this structure is maintained in GPU driver structure.
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*/
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struct nvgpu_gr {
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/**
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* Pointer to GPU driver struct.
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*/
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struct gk20a *g;
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/**
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* Condition variable for GR initialization.
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* Waiters shall wait on this condition to ensure GR engine
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* is initialized.
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*/
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struct nvgpu_cond init_wq;
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/**
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* Flag to indicate if GR engine is initialized.
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*/
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bool initialized;
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/**
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* Pointer to global context buffer descriptor structure.
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*/
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struct nvgpu_gr_global_ctx_buffer_desc *global_ctx_buffer;
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/**
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* Pointer to Golden context image structure.
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*/
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struct nvgpu_gr_obj_ctx_golden_image *golden_image;
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/**
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* Pointer to GR context descriptor structure.
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*/
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struct nvgpu_gr_ctx_desc *gr_ctx_desc;
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/**
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* Pointer to GR configuration structure.
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*/
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struct nvgpu_gr_config *config;
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/**
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* Pointer to GR falcon data structure.
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*/
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struct nvgpu_gr_falcon *falcon;
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/**
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* Pointer to GR interrupt data structure.
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*/
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struct nvgpu_gr_intr *intr;
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/**
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* Function pointer to remove GR s/w support.
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*/
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void (*remove_support)(struct gk20a *g);
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/**
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* Flag to indicate GR s/w has been initialized.
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*/
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bool sw_ready;
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#ifdef CONFIG_NVGPU_DEBUGGER
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struct nvgpu_gr_hwpm_map *hwpm_map;
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#endif
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#ifdef CONFIG_NVGPU_GRAPHICS
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struct nvgpu_gr_zcull *zcull;
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struct nvgpu_gr_zbc *zbc;
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#endif
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#ifdef CONFIG_NVGPU_NON_FUSA
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u32 fecs_feature_override_ecc_val;
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#endif
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#ifdef CONFIG_NVGPU_CILP
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u32 cilp_preempt_pending_chid;
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#endif
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#if defined(CONFIG_NVGPU_RECOVERY) || defined(CONFIG_NVGPU_DEBUGGER)
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struct nvgpu_mutex ctxsw_disable_mutex;
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int ctxsw_disable_count;
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#endif
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};
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#endif /* NVGPU_GR_PRIV_H */
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