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Add change sequencer for PS3.5 Add HAL to select if change sequencer is neeeded. Add calls from pstate.c to change sequence sw and pmu setup. JIRA NVGPU-1157 Change-Id: I0722c4bf875577ba04f56f49f21cb1a149b1d37b Reviewed-on: https://git-master.nvidia.com/r/1929788 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1950409 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
64 lines
2.2 KiB
C
64 lines
2.2 KiB
C
/*
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* general clock structures & definitions
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*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_CHANGE_SEQ_H
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#define NVGPU_CHANGE_SEQ_H
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#include <nvgpu/boardobjgrpmask.h>
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struct change_seq_pmu_script {
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struct perf_change_seq_pmu_script buf;
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u32 super_surface_offset;
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};
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struct change_seq {
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u8 version;
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bool b_enabled_pmu_support;
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u32 thread_seq_id_last;
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u64 thread_carry_over_timens;
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struct ctrl_perf_change_seq_change last_pstate_values;
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struct boardobjgrpmask_e32 clk_domains_exclusion_mask;
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struct boardobjgrpmask_e32 clk_domains_inclusion_mask;
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u32 client_lock_mask;
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};
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struct change_seq_pmu {
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struct change_seq super;
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bool b_lock;
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bool b_vf_point_check_ignore;
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u32 cpu_adverised_step_id_mask;
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u32 cpu_step_id_mask;
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u32 event_mask_pending;
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u32 event_mask_received;
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u32 last_completed_change_Seq_id;
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struct change_seq_pmu_script script_curr;
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struct change_seq_pmu_script script_last;
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struct change_seq_pmu_script script_query;
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};
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int nvgpu_perf_change_seq_sw_setup(struct gk20a *g);
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int nvgpu_perf_change_seq_pmu_setup(struct gk20a *g);
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#endif /* NVGPU_CHANGE_SEQ_H */
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