mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 09:12:24 +03:00
398a30a546
Changes
1. Created gsp hal function to read the hardware config register
to tell whether the board is debug fused.
2. Created function to get the binary file names as per debug fuse.
NVGPU-9295
Bug 3897331
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Change-Id: Ia8462aa6f3d8d0d538c06f35245c965e106b3d37
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2822443
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
58 lines
2.4 KiB
C
58 lines
2.4 KiB
C
/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef GSP_GA10B_H
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#define GSP_GA10B_H
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u32 ga10b_gsp_falcon_base_addr(void);
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u32 ga10b_gsp_falcon2_base_addr(void);
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int ga10b_gsp_engine_reset(struct gk20a *g);
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bool ga10b_gsp_validate_mem_integrity(struct gk20a *g);
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bool ga10b_gsp_is_debug_mode_en(struct gk20a *g);
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#ifdef CONFIG_NVGPU_GSP_SCHEDULER
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void ga10b_gsp_flcn_setup_boot_config(struct gk20a *g);
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/* queue */
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u32 ga10b_gsp_queue_head_r(u32 i);
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u32 ga10b_gsp_queue_head__size_1_v(void);
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u32 ga10b_gsp_queue_tail_r(u32 i);
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u32 ga10b_gsp_queue_tail__size_1_v(void);
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int ga10b_gsp_queue_head(struct gk20a *g, u32 queue_id, u32 queue_index,
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u32 *head, bool set);
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int ga10b_gsp_queue_tail(struct gk20a *g, u32 queue_id, u32 queue_index,
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u32 *tail, bool set);
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void ga10b_gsp_msgq_tail(struct gk20a *g, struct nvgpu_gsp *gsp,
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u32 *tail, bool set);
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int ga10b_gsp_flcn_copy_to_emem(struct gk20a *g,
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u32 dst, u8 *src, u32 size, u8 port);
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int ga10b_gsp_flcn_copy_from_emem(struct gk20a *g,
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u32 src, u8 *dst, u32 size, u8 port);
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/* interrupt */
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void ga10b_gsp_enable_irq(struct gk20a *g, bool enable);
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s32 ga10b_gsp_get_emem_boundaries(struct gk20a *g,
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u32 *start_emem, u32 *end_emem);
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void ga10b_gsp_isr(struct gk20a *g, struct nvgpu_gsp *gsp);
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void ga10b_gsp_set_msg_intr(struct gk20a *g);
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#endif /* CONFIG_NVGPU_GSP_SCHEDULER */
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#endif /* GSP_GA10B_H */
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