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66f7bcc2f8
NVHSCLK registers used by NVLINK IP are part of dev_top hardware headers. This patch adds "Top" as a separate unit and exposes HALs to access dev_top registers. The top unit contains top-level configuration information and any extra registers or features that do not fit into another block's feature set. JIRA NVGPU-1053 JIRA NVGPU-966 Change-Id: Id9a43d4a1c5397959897a242ea97a39a1b95f916 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1803632 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
38 lines
1.5 KiB
C
38 lines
1.5 KiB
C
/*
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* GV100 TOP UNIT
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*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef TOP_GV100_H
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#define TOP_GV100_H
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#include <nvgpu/types.h>
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struct gk20a;
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u32 gv100_top_get_nvhsclk_ctrl_e_clk_nvl(struct gk20a *g);
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void gv100_top_set_nvhsclk_ctrl_e_clk_nvl(struct gk20a *g, u32 val);
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u32 gv100_top_get_nvhsclk_ctrl_swap_clk_nvl(struct gk20a *g);
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void gv100_top_set_nvhsclk_ctrl_swap_clk_nvl(struct gk20a *g, u32 val);
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#endif
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