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JIRA DNVGPU-123 Function will copy possible clock points for a given master clock domain to pointer passed. pointer with NULL value and count of zero can be passed to query number of clock points for a given domain so that memory can be allocated and function called again to fill clock points Change-Id: Iec6206f23789980036be99793599e934bd221035 Reviewed-on: http://git-master/r/1218912 (cherry picked from commit 9219697bff1e12deb605325055a02a7b387996e9) Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1235055 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
103 lines
3.0 KiB
C
103 lines
3.0 KiB
C
/*
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* general clock structures & definitions
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*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _CLK_H_
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#define _CLK_H_
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#include "clk_vin.h"
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#include "clk_fll.h"
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#include "clk_domain.h"
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#include "clk_prog.h"
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#include "clk_vf_point.h"
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#include "clk_mclk.h"
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#include "gk20a/gk20a.h"
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#define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SKIP 0x10
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#define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_MASK 0x1F
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#define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SHIFT 0
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/* clock related defines for GPUs supporting clock control from pmu*/
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struct clk_pmupstate {
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struct avfsvinobjs avfs_vinobjs;
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struct avfsfllobjs avfs_fllobjs;
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struct clk_domains clk_domainobjs;
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struct clk_progs clk_progobjs;
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struct clk_vf_points clk_vf_pointobjs;
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struct clk_mclk_state clk_mclk;
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};
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struct clockentry {
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u8 vbios_clk_domain;
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u8 clk_which;
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u8 perf_index;
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u32 api_clk_domain;
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};
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_MAX_NUMCLKS 9
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struct vbios_clock_domain {
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u8 clock_type;
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u8 num_domains;
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struct clockentry clock_entry[NV_PERF_HEADER_4X_CLOCKS_DOMAINS_MAX_NUMCLKS];
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};
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struct vbios_clocks_table_1x_hal_clock_entry {
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enum nv_pmu_clk_clkwhich domain;
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bool b_noise_aware_capable;
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};
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_GPC2CLK 0
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_XBAR2CLK 1
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_DRAMCLK 2
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_SYS2CLK 3
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_HUB2CLK 4
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_MSDCLK 5
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_PWRCLK 6
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_DISPCLK 7
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_NUMCLKS 8
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#define PERF_CLK_MCLK 0
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#define PERF_CLK_DISPCLK 1
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#define PERF_CLK_GPC2CLK 2
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#define PERF_CLK_HOSTCLK 3
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#define PERF_CLK_LTC2CLK 4
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#define PERF_CLK_SYS2CLK 5
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#define PERF_CLK_HUB2CLK 6
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#define PERF_CLK_LEGCLK 7
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#define PERF_CLK_MSDCLK 8
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#define PERF_CLK_XCLK 9
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#define PERF_CLK_PWRCLK 10
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#define PERF_CLK_XBAR2CLK 11
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#define PERF_CLK_PCIEGENCLK 12
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#define PERF_CLK_NUM 13
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u32 clk_pmu_vf_inject(struct gk20a *g);
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u32 clk_pmu_vin_load(struct gk20a *g);
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u32 clk_domain_print_vf_table(struct gk20a *g, u32 clkapidomain);
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u32 clk_domain_get_f_or_v
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(
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struct gk20a *g,
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u32 clkapidomain,
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u16 *pclkmhz,
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u32 *pvoltuv
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);
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u32 clk_domain_get_f_points(
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struct gk20a *g,
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u32 clkapidomain,
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u32 *fpointscount,
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u16 *freqpointsinmhz
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);
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#endif
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