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3c3f80a687
MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in nvgpu by renaming them to follow the convention,'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition between file name and directory or 'NVGPU_HEADER-NAME' when there is repetition. JIRA NVGPU-1028 Change-Id: I8a473c6c1a864f3893920d8e06e305095e523d2a Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809082 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
78 lines
2.3 KiB
C
78 lines
2.3 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_VOLT_DEV_H
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#define NVGPU_VOLT_DEV_H
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#include "boardobj/boardobj.h"
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#include "boardobj/boardobjgrp.h"
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#include "ctrl/ctrlvolt.h"
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#define VOLTAGE_TABLE_MAX_ENTRIES_ONE 1
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#define VOLTAGE_TABLE_MAX_ENTRIES 256
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struct voltage_device {
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struct boardobj super;
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u8 volt_domain;
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u8 i2c_dev_idx;
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u32 switch_delay_us;
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u32 num_entries;
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struct voltage_device_entry *pentry[VOLTAGE_TABLE_MAX_ENTRIES];
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struct voltage_device_entry *pcurr_entry;
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u8 rsvd_0;
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u8 rsvd_1;
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u8 operation_type;
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u32 voltage_min_uv;
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u32 voltage_max_uv;
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u32 volt_step_uv;
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};
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struct voltage_device_entry {
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u32 voltage_uv;
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};
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struct voltage_device_metadata {
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struct boardobjgrp_e32 volt_devices;
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};
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/*!
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* Extends VOLTAGE_DEVICE providing attributes specific to PWM controllers.
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*/
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struct voltage_device_pwm {
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struct voltage_device super;
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s32 voltage_base_uv;
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s32 voltage_offset_scale_uv;
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enum nv_pmu_pmgr_pwm_source source;
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u32 raw_period;
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};
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struct voltage_device_pwm_entry {
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struct voltage_device_entry super;
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u32 duty_cycle;
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};
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/* PWM end */
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u32 volt_dev_sw_setup(struct gk20a *g);
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int volt_dev_pmu_setup(struct gk20a *g);
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#endif /* NVGPU_VOLT_DEV_H */
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