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3c980954c4
Add command post support to send commands to GSP nvriscv. NVGPU-6784 Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com> Change-Id: Ib7fde3712c24a5b4f0f58d7788e67d29a1e351a2 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2590763 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
60 lines
1.9 KiB
C
60 lines
1.9 KiB
C
/*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GSP_CMD_IF_H
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#define NVGPU_GSP_CMD_IF_H
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#include <nvgpu/types.h>
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#include "gsp_seq.h"
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struct gk20a;
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#define GSP_NV_CMDQ_LOG_ID 0U
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#define GSP_NV_CMDQ_LOG_ID__LAST 0U
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#define GSP_NV_MSGQ_LOG_ID 1U
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#define NV_GSP_UNIT_REWIND NV_FLCN_UNIT_ID_REWIND
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#define NV_GSP_UNIT_NULL 0x01U
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#define NV_GSP_UNIT_INIT 0x02U
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#define NV_GSP_UNIT_END 0x0AU
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#define GSP_MSG_HDR_SIZE U32(sizeof(struct gsp_hdr))
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#define GSP_CMD_HDR_SIZE U32(sizeof(struct gsp_hdr))
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struct gsp_hdr {
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u8 unit_id;
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u8 size;
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u8 ctrl_flags;
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u8 seq_id;
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};
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struct nv_flcn_cmd_gsp {
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struct gsp_hdr hdr;
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};
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u8 gsp_unit_id_is_valid(u8 id);
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/* command handling methods*/
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int nvgpu_gsp_cmd_post(struct gk20a *g, struct nv_flcn_cmd_gsp *cmd,
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u32 queue_id, gsp_callback callback, void *cb_param, u32 timeout);
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#endif /* NVGPU_GSP_CMD_IF_H */
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