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3d9c33c595
Add clock arbiter skeleton with support of clock sessions, notifications on clock changes, request numbering, and asynchronous handling of clock requests. Provides minimum behaviour to allow unit tests implementation. Actual arbitration and clock settings will be done separately. For now, dummy arbiter keeps last requested target mhz. Actual arbiter may move to a lockless implementation. Jira DNVGPU-125 Change-Id: I6a8e443fb0d15dc5f1993e7260256d71acddd106 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1223476 (cherry picked from commit cb130825d84e4124d273bd443e2b62d493377461) Reviewed-on: http://git-master/r/1243105 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
242 lines
6.2 KiB
C
242 lines
6.2 KiB
C
/*
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* GP106 HAL interface
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*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/types.h>
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#include <linux/printk.h>
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#include <linux/types.h>
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#include "gk20a/gk20a.h"
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#include "gp10b/gr_gp10b.h"
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#include "gp10b/mc_gp10b.h"
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#include "gp106/ltc_gp106.h"
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#include "gp10b/mm_gp10b.h"
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#include "gp10b/ce_gp10b.h"
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#include "gp106/fifo_gp106.h"
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#include "gp106/regops_gp106.h"
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#include "gp10b/cde_gp10b.h"
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#include "gp106/therm_gp106.h"
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#include "gp106/xve_gp106.h"
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#include "gp106/bios_gp106.h"
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#include "gm20b/gr_gm20b.h"
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#include "gm20b/fifo_gm20b.h"
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#include "gm20b/pmu_gm20b.h"
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#include "gp106/clk_gp106.h"
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#include "gp106/clk_arb_gp106.h"
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#include "gp106/mm_gp106.h"
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#include "gp106/pmu_gp106.h"
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#include "gp106/gr_ctx_gp106.h"
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#include "gp106/gr_gp106.h"
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#include "gp106/fb_gp106.h"
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#include "gp106/gp106_gating_reglist.h"
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#include "nvgpu_gpuid_t18x.h"
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#include "hw_proj_gp106.h"
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#include "gk20a/dbg_gpu_gk20a.h"
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#include "gk20a/css_gr_gk20a.h"
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static struct gpu_ops gp106_ops = {
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.clock_gating = {
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.slcg_bus_load_gating_prod =
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gp106_slcg_bus_load_gating_prod,
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.slcg_ce2_load_gating_prod =
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gp106_slcg_ce2_load_gating_prod,
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.slcg_chiplet_load_gating_prod =
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gp106_slcg_chiplet_load_gating_prod,
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.slcg_ctxsw_firmware_load_gating_prod =
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gp106_slcg_ctxsw_firmware_load_gating_prod,
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.slcg_fb_load_gating_prod =
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gp106_slcg_fb_load_gating_prod,
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.slcg_fifo_load_gating_prod =
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gp106_slcg_fifo_load_gating_prod,
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.slcg_gr_load_gating_prod =
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gr_gp106_slcg_gr_load_gating_prod,
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.slcg_ltc_load_gating_prod =
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ltc_gp106_slcg_ltc_load_gating_prod,
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.slcg_perf_load_gating_prod =
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gp106_slcg_perf_load_gating_prod,
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.slcg_priring_load_gating_prod =
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gp106_slcg_priring_load_gating_prod,
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.slcg_pmu_load_gating_prod =
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gp106_slcg_pmu_load_gating_prod,
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.slcg_therm_load_gating_prod =
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gp106_slcg_therm_load_gating_prod,
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.slcg_xbar_load_gating_prod =
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gp106_slcg_xbar_load_gating_prod,
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.blcg_bus_load_gating_prod =
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gp106_blcg_bus_load_gating_prod,
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.blcg_ce_load_gating_prod =
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gp106_blcg_ce_load_gating_prod,
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.blcg_fb_load_gating_prod =
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gp106_blcg_fb_load_gating_prod,
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.blcg_fifo_load_gating_prod =
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gp106_blcg_fifo_load_gating_prod,
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.blcg_gr_load_gating_prod =
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gp106_blcg_gr_load_gating_prod,
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.blcg_ltc_load_gating_prod =
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gp106_blcg_ltc_load_gating_prod,
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.blcg_pmu_load_gating_prod =
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gp106_blcg_pmu_load_gating_prod,
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.blcg_xbar_load_gating_prod =
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gp106_blcg_xbar_load_gating_prod,
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.pg_gr_load_gating_prod =
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gr_gp106_pg_gr_load_gating_prod,
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}
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};
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static int gp106_get_litter_value(struct gk20a *g, int value)
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{
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int ret = -EINVAL;
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switch (value) {
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case GPU_LIT_NUM_GPCS:
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ret = proj_scal_litter_num_gpcs_v();
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break;
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case GPU_LIT_NUM_PES_PER_GPC:
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ret = proj_scal_litter_num_pes_per_gpc_v();
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break;
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case GPU_LIT_NUM_ZCULL_BANKS:
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ret = proj_scal_litter_num_zcull_banks_v();
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break;
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case GPU_LIT_NUM_TPC_PER_GPC:
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ret = proj_scal_litter_num_tpc_per_gpc_v();
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break;
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case GPU_LIT_NUM_FBPS:
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ret = proj_scal_litter_num_fbps_v();
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break;
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case GPU_LIT_GPC_BASE:
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ret = proj_gpc_base_v();
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break;
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case GPU_LIT_GPC_STRIDE:
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ret = proj_gpc_stride_v();
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break;
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case GPU_LIT_GPC_SHARED_BASE:
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ret = proj_gpc_shared_base_v();
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break;
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case GPU_LIT_TPC_IN_GPC_BASE:
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ret = proj_tpc_in_gpc_base_v();
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break;
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case GPU_LIT_TPC_IN_GPC_STRIDE:
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ret = proj_tpc_in_gpc_stride_v();
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break;
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case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
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ret = proj_tpc_in_gpc_shared_base_v();
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break;
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case GPU_LIT_PPC_IN_GPC_BASE:
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ret = proj_ppc_in_gpc_base_v();
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break;
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case GPU_LIT_PPC_IN_GPC_STRIDE:
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ret = proj_ppc_in_gpc_stride_v();
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break;
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case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
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ret = proj_ppc_in_gpc_shared_base_v();
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break;
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case GPU_LIT_ROP_BASE:
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ret = proj_rop_base_v();
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break;
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case GPU_LIT_ROP_STRIDE:
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ret = proj_rop_stride_v();
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break;
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case GPU_LIT_ROP_SHARED_BASE:
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ret = proj_rop_shared_base_v();
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break;
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case GPU_LIT_HOST_NUM_ENGINES:
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ret = proj_host_num_engines_v();
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break;
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case GPU_LIT_HOST_NUM_PBDMA:
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ret = proj_host_num_pbdma_v();
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break;
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case GPU_LIT_LTC_STRIDE:
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ret = proj_ltc_stride_v();
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break;
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case GPU_LIT_LTS_STRIDE:
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ret = proj_lts_stride_v();
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break;
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case GPU_LIT_NUM_FBPAS:
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ret = proj_scal_litter_num_fbpas_v();
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break;
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case GPU_LIT_FBPA_SHARED_BASE:
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ret = proj_fbpa_shared_base_v();
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break;
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case GPU_LIT_FBPA_BASE:
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ret = proj_fbpa_base_v();
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break;
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case GPU_LIT_FBPA_STRIDE:
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ret = proj_fbpa_stride_v();
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break;
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default:
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BUG();
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break;
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}
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return ret;
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}
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int gp106_init_hal(struct gk20a *g)
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{
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struct gpu_ops *gops = &g->ops;
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struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
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gk20a_dbg_fn("");
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*gops = gp106_ops;
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gops->privsecurity = 1;
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gops->securegpccs = 1;
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gops->pmupstate = true;
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gp10b_init_mc(gops);
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gp106_init_gr(gops);
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gp106_init_ltc(gops);
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gp106_init_fb(gops);
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gp106_init_fifo(gops);
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gp10b_init_ce(gops);
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gp106_init_gr_ctx(gops);
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gp106_init_mm(gops);
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gp106_init_pmu_ops(gops);
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gk20a_init_debug_ops(gops);
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gk20a_init_dbg_session_ops(gops);
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gp106_init_clk_ops(gops);
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gp106_init_clk_arb_ops(gops);
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gp106_init_regops(gops);
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gp10b_init_cde_ops(gops);
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gk20a_init_tsg_ops(gops);
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#if defined(CONFIG_GK20A_CYCLE_STATS)
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gk20a_init_css_ops(gops);
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#endif
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gp106_init_bios(gops);
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gp106_init_therm_ops(gops);
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gp106_init_xve_ops(gops);
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gops->name = "gp10x";
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gops->get_litter_value = gp106_get_litter_value;
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gops->chip_init_gpu_characteristics = gk20a_init_gpu_characteristics;
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gops->gr_ctx.use_dma_for_fw_bootstrap = true;
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gops->read_ptimer = gk20a_read_ptimer;
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c->twod_class = FERMI_TWOD_A;
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c->threed_class = PASCAL_B;
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c->compute_class = PASCAL_COMPUTE_B;
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c->gpfifo_class = PASCAL_CHANNEL_GPFIFO_A;
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c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B;
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c->dma_copy_class = PASCAL_DMA_COPY_A;
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gk20a_dbg_fn("done");
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return 0;
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}
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