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git://nv-tegra.nvidia.com/linux-nvgpu.git
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3d9c33c595
Add clock arbiter skeleton with support of clock sessions, notifications on clock changes, request numbering, and asynchronous handling of clock requests. Provides minimum behaviour to allow unit tests implementation. Actual arbitration and clock settings will be done separately. For now, dummy arbiter keeps last requested target mhz. Actual arbiter may move to a lockless implementation. Jira DNVGPU-125 Change-Id: I6a8e443fb0d15dc5f1993e7260256d71acddd106 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1223476 (cherry picked from commit cb130825d84e4124d273bd443e2b62d493377461) Reviewed-on: http://git-master/r/1243105 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
398 lines
8.4 KiB
C
398 lines
8.4 KiB
C
/*
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* general p state infrastructure
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*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include "gk20a/gk20a.h"
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#include "clk/clk.h"
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#include "perf/perf.h"
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#include "pmgr/pmgr.h"
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#include "include/bios.h"
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#include "pstate/pstate.h"
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#include "therm/thrm.h"
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static int pstate_sw_setup(struct gk20a *g);
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/*sw setup for pstate components*/
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int gk20a_init_pstate_support(struct gk20a *g)
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{
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u32 err;
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gk20a_dbg_fn("");
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err = volt_rail_sw_setup(g);
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if (err)
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return err;
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err = volt_dev_sw_setup(g);
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if (err)
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return err;
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err = volt_policy_sw_setup(g);
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if (err)
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return err;
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err = clk_vin_sw_setup(g);
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if (err)
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return err;
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err = clk_fll_sw_setup(g);
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if (err)
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return err;
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err = therm_domain_sw_setup(g);
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if (err)
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return err;
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err = vfe_var_sw_setup(g);
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if (err)
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return err;
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err = vfe_equ_sw_setup(g);
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if (err)
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return err;
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err = clk_domain_sw_setup(g);
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if (err)
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return err;
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err = clk_vf_point_sw_setup(g);
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if (err)
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return err;
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err = clk_prog_sw_setup(g);
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if (err)
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return err;
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err = pstate_sw_setup(g);
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if (err)
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return err;
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err = pmgr_domain_sw_setup(g);
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return err;
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}
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/*sw setup for pstate components*/
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int gk20a_init_pstate_pmu_support(struct gk20a *g)
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{
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u32 err;
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gk20a_dbg_fn("");
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err = volt_rail_pmu_setup(g);
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if (err)
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return err;
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err = volt_dev_pmu_setup(g);
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if (err)
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return err;
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err = volt_policy_pmu_setup(g);
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if (err)
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return err;
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err = volt_pmu_send_load_cmd_to_pmu(g);
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if (err) {
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gk20a_err(dev_from_gk20a(g),
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"Failed to send VOLT LOAD CMD to PMU: status = 0x%08x.",
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err);
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return err;
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}
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err = therm_domain_pmu_setup(g);
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if (err)
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return err;
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err = vfe_var_pmu_setup(g);
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if (err)
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return err;
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err = vfe_equ_pmu_setup(g);
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if (err)
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return err;
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err = clk_domain_pmu_setup(g);
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if (err)
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return err;
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err = clk_prog_pmu_setup(g);
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if (err)
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return err;
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err = clk_vin_pmu_setup(g);
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if (err)
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return err;
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err = clk_fll_pmu_setup(g);
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if (err)
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return err;
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err = clk_vf_point_pmu_setup(g);
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if (err)
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return err;
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err = clk_pmu_vin_load(g);
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if (err)
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return err;
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err = perf_pmu_vfe_load(g);
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if (err)
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return err;
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err = clk_vf_point_cache(g);
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if (err)
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return err;
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err = clk_set_boot_fll_clk(g);
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if (err)
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return err;
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err = pmgr_domain_pmu_setup(g);
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return err;
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}
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int pstate_construct_super(struct gk20a *g, struct boardobj **ppboardobj,
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u16 size, void *args)
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{
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struct pstate *ptmppstate = (struct pstate *)args;
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struct pstate *pstate;
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int err;
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err = boardobj_construct_super(g, ppboardobj, size, args);
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if (err)
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return err;
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pstate = (struct pstate *)*ppboardobj;
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pstate->num = ptmppstate->num;
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pstate->clklist = ptmppstate->clklist;
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return 0;
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}
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int pstate_construct_3x(struct gk20a *g, struct boardobj **ppboardobj,
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u16 size, void *args)
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{
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struct boardobj *ptmpobj = (struct boardobj *)args;
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ptmpobj->type_mask |= BIT(CTRL_PERF_PSTATE_TYPE_3X);
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return pstate_construct_super(g, ppboardobj, size, args);
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}
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struct pstate *pstate_construct(struct gk20a *g, void *args)
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{
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struct pstate *pstate = NULL;
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struct pstate *tmp = (struct pstate *)args;
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if ((tmp->super.type != CTRL_PERF_PSTATE_TYPE_3X) ||
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(pstate_construct_3x(g, (struct boardobj **)&pstate,
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sizeof(struct pstate), args)))
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gk20a_err(dev_from_gk20a(g),
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"error constructing pstate num=%u", tmp->num);
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return pstate;
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}
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int pstate_insert(struct gk20a *g, struct pstate *pstate, int index)
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{
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struct pstates *pstates = &(g->perf_pmu.pstatesobjs);
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int err;
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err = boardobjgrp_objinsert(&pstates->super.super,
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(struct boardobj *)pstate, index);
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if (err) {
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gk20a_err(dev_from_gk20a(g),
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"error adding pstate boardobj %d", index);
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return err;
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}
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pstates->num_levels++;
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return err;
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}
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static int parse_pstate_entry_5x(struct gk20a *g,
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struct vbios_pstate_header_5x *hdr,
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struct vbios_pstate_entry_5x *entry,
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struct pstate *pstate)
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{
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u8 *p = (u8 *)entry;
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u32 clkidx;
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p += hdr->base_entry_size;
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memset(pstate, 0, sizeof(struct pstate));
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pstate->super.type = CTRL_PERF_PSTATE_TYPE_3X;
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pstate->num = 0x0F - entry->pstate_level;
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pstate->clklist.num_info = hdr->clock_entry_count;
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gk20a_dbg_info("pstate P%u", pstate->num);
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for (clkidx = 0; clkidx < hdr->clock_entry_count; clkidx++) {
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struct clk_set_info *pclksetinfo;
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struct vbios_pstate_entry_clock_5x *clk_entry;
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struct clk_domain *clk_domain;
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clk_domain = (struct clk_domain *)BOARDOBJGRP_OBJ_GET_BY_IDX(
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&g->clk_pmu.clk_domainobjs.super.super, clkidx);
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pclksetinfo = &pstate->clklist.clksetinfo[clkidx];
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clk_entry = (struct vbios_pstate_entry_clock_5x *)p;
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pclksetinfo->clkwhich = clk_domain->domain;
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pclksetinfo->nominal_mhz =
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BIOS_GET_FIELD(clk_entry->param0,
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VBIOS_PSTATE_5X_CLOCK_PROG_PARAM0_NOM_FREQ_MHZ);
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pclksetinfo->min_mhz =
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BIOS_GET_FIELD(clk_entry->param1,
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VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MIN_FREQ_MHZ);
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pclksetinfo->max_mhz =
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BIOS_GET_FIELD(clk_entry->param1,
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VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ);
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gk20a_dbg_info(
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"clk_domain=%u nominal_mhz=%u min_mhz=%u max_mhz=%u",
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pclksetinfo->clkwhich, pclksetinfo->nominal_mhz,
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pclksetinfo->min_mhz, pclksetinfo->max_mhz);
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p += hdr->clock_entry_size;
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}
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return 0;
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}
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static int parse_pstate_table_5x(struct gk20a *g,
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struct vbios_pstate_header_5x *hdr)
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{
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struct pstate _pstate, *pstate = &_pstate;
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struct vbios_pstate_entry_5x *entry;
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u32 entry_size;
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u8 i;
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u8 *p = (u8 *)hdr;
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int err = 0;
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if ((hdr->header_size != VBIOS_PSTATE_HEADER_5X_SIZE_10) ||
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(hdr->base_entry_count == 0) ||
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((hdr->base_entry_size != VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_2) &&
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(hdr->base_entry_size != VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_3)) ||
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(hdr->clock_entry_size != VBIOS_PSTATE_CLOCK_ENTRY_5X_SIZE_6) ||
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(hdr->clock_entry_count > CLK_SET_INFO_MAX_SIZE))
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return -EINVAL;
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p += hdr->header_size;
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entry_size = hdr->base_entry_size +
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hdr->clock_entry_count * hdr->clock_entry_size;
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for (i = 0; i < hdr->base_entry_count; i++, p += entry_size) {
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entry = (struct vbios_pstate_entry_5x *)p;
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if (entry->pstate_level == VBIOS_PERFLEVEL_SKIP_ENTRY)
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continue;
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err = parse_pstate_entry_5x(g, hdr, entry, pstate);
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if (err)
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goto done;
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pstate = pstate_construct(g, pstate);
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if (!pstate)
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goto done;
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err = pstate_insert(g, pstate, i);
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if (err)
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goto done;
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}
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done:
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return err;
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}
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static int pstate_sw_setup(struct gk20a *g)
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{
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struct vbios_pstate_header_5x *hdr = NULL;
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int err = 0;
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gk20a_dbg_fn("");
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err = boardobjgrpconstruct_e32(&g->perf_pmu.pstatesobjs.super);
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if (err) {
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gk20a_err(dev_from_gk20a(g),
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"error creating boardobjgrp for pstates, err=%d",
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err);
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goto done;
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}
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if (g->ops.bios.get_perf_table_ptrs) {
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hdr = (struct vbios_pstate_header_5x *)
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g->ops.bios.get_perf_table_ptrs(g,
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g->bios.perf_token, PERFORMANCE_TABLE);
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}
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if (!hdr) {
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gk20a_err(dev_from_gk20a(g),
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"performance table not found");
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err = -EINVAL;
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goto done;
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}
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if (hdr->version != VBIOS_PSTATE_TABLE_VERSION_5X) {
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gk20a_err(dev_from_gk20a(g),
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"unknown/unsupported clocks table version=0x%02x",
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hdr->version);
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err = -EINVAL;
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goto done;
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}
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err = parse_pstate_table_5x(g, hdr);
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done:
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return err;
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}
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static struct pstate *pstate_find(struct gk20a *g, u32 num)
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{
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struct pstates *pstates = &(g->perf_pmu.pstatesobjs);
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struct pstate *pstate;
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u8 i;
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gk20a_dbg_info("pstates = %p", pstates);
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BOARDOBJGRP_FOR_EACH(&pstates->super.super,
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struct pstate *, pstate, i) {
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gk20a_dbg_info("pstate=%p num=%u (looking for num=%u)",
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pstate, pstate->num, num);
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if (pstate->num == num)
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return pstate;
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}
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return NULL;
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}
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struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g,
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u32 pstate_num, enum nv_pmu_clk_clkwhich clkwhich)
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{
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struct pstate *pstate = pstate_find(g, pstate_num);
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struct clk_set_info *info;
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u32 clkidx;
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gk20a_dbg_info("pstate = %p", pstate);
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if (!pstate)
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return NULL;
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for (clkidx = 0; clkidx < pstate->clklist.num_info; clkidx++) {
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info = &pstate->clklist.clksetinfo[clkidx];
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if (info->clkwhich == clkwhich)
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return info;
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}
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return NULL;
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}
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