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3d9c67a0e7fca0ba44d57a094d37f62017a1b0a2
linux-nvgpu/drivers/gpu/nvgpu/common/power_features/cg/cg.c
Deepak Nibade 3d9c67a0e7 gpu: nvgpu: enable Orin support in safety build 
Most of the Orin chip specific code is compiled out of safety build
with CONFIG_NVGPU_NON_FUSA and CONFIG_NVGPU_HAL_NON_FUSA. Remove the
config protection from Orin/GA10B specific code. Currently all code
is enabled. Code not required in safety will be compiled out later
in separate activity.

Other noteworthy changes in this patch related to safety build:

- In ga10b_ce_request_idle(), add a log print to dump num_pce so that
  compiler does not complain about unused variable num_pce.
- In ga10b_fifo_ctxsw_timeout_isr(), protect variables active_eng_id and
  recover under CONFIG_NVGPU_KERNEL_MODE_SUBMIT to fix compilation
  errors of unused variables.
- Compile out HAL gops.pbdma.force_ce_split() from safety since this HAL
  is GA100 specific and not required for GA10B.
- Compile out gr_ga100_process_context_buffer_priv_segment() with
  CONFIG_NVGPU_DEBUGGER.
- Compile out VAB support with CONFIG_NVGPU_HAL_NON_FUSA.
- In ga10b_gr_intr_handle_sw_method(), protect left_shift_by_2 variable
  with appropriate configs to fix unused variable compilation error.
- In ga10b_intr_isr_stall_host2soc_3(), compile ELPG function calls
  with CONFIG_NVGPU_POWER_PG.
- In ga10b_pmu_handle_swgen1_irq(), move whole function body under
  CONFIG_NVGPU_FALCON_DEBUG to fix unused variable compilation errors.
- Add below TU104 specific files in safety build since some of the code
  in those files is required for GA10B. Unnecessary code will be
  compiled out later on.
	hal/gr/init/gr_init_tu104.c
	hal/class/class_tu104.c
	hal/mc/mc_tu104.c
	hal/fifo/usermode_tu104.c
	hal/gr/falcon/gr_falcon_tu104.c
- Compile out GA10B specific debugger/profiler related files from
  safety build.
- Disable CONFIG_NVGPU_FALCON_DEBUG from safety debug build temporarily
  to work around compilation errors seen with keeping this config
  enabled. Config will be re-enabled in safety debug build later.

Jira NVGPU-7276

Change-Id: I35f2489830ac083d52504ca411c3f1d96e72fc48
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2627048
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-11-26 08:46:47 -08:00

655 lines
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/*
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/engines.h>
#include <nvgpu/device.h>
#include <nvgpu/enabled.h>
#include <nvgpu/power_features/cg.h>
static void nvgpu_cg_set_mode(struct gk20a *g, u32 cgmode, u32 mode_config)
{
u32 n;
u32 engine_id = 0;
const struct nvgpu_device *dev = NULL;
struct nvgpu_fifo *f = &g->fifo;
nvgpu_log_fn(g, " ");
for (n = 0; n < f->num_engines; n++) {
dev = f->active_engines[n];
#ifdef CONFIG_NVGPU_NON_FUSA
/* gr_engine supports both BLCG and ELCG */
if ((cgmode == BLCG_MODE) &&
(dev->type == NVGPU_DEVTYPE_GRAPHICS)) {
g->ops.therm.init_blcg_mode(g, (u32)mode_config,
engine_id);
break;
} else
#endif
if (cgmode == ELCG_MODE) {
g->ops.therm.init_elcg_mode(g, (u32)mode_config,
dev->engine_id);
} else {
nvgpu_err(g, "invalid cg mode %d, config %d for "
"engine_id %d",
cgmode, mode_config, engine_id);
}
}
}
void nvgpu_cg_elcg_enable_no_wait(struct gk20a *g)
{
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, " ");
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (g->elcg_enabled) {
nvgpu_cg_set_mode(g, ELCG_MODE, ELCG_AUTO);
}
nvgpu_mutex_release(&g->cg_pg_lock);
}
void nvgpu_cg_elcg_disable_no_wait(struct gk20a *g)
{
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, " ");
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (g->elcg_enabled) {
nvgpu_cg_set_mode(g, ELCG_MODE, ELCG_RUN);
}
nvgpu_mutex_release(&g->cg_pg_lock);
}
void nvgpu_cg_blcg_fb_ltc_load_enable(struct gk20a *g)
{
nvgpu_log_fn(g, " ");
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (!g->blcg_enabled) {
goto done;
}
if (g->ops.cg.blcg_fb_load_gating_prod != NULL) {
g->ops.cg.blcg_fb_load_gating_prod(g, true);
}
if (g->ops.cg.blcg_ltc_load_gating_prod != NULL) {
g->ops.cg.blcg_ltc_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
}
void nvgpu_cg_blcg_fifo_load_enable(struct gk20a *g)
{
nvgpu_log_fn(g, " ");
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (!g->blcg_enabled) {
goto done;
}
if (g->ops.cg.blcg_fifo_load_gating_prod != NULL) {
g->ops.cg.blcg_fifo_load_gating_prod(g, true);
}
if (g->ops.cg.blcg_runlist_load_gating_prod != NULL) {
g->ops.cg.blcg_runlist_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
}
void nvgpu_cg_blcg_pmu_load_enable(struct gk20a *g)
{
nvgpu_log_fn(g, " ");
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (!g->blcg_enabled) {
goto done;
}
if (g->ops.cg.blcg_pmu_load_gating_prod != NULL) {
g->ops.cg.blcg_pmu_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
}
void nvgpu_cg_blcg_ce_load_enable(struct gk20a *g)
{
nvgpu_log_fn(g, " ");
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (!g->blcg_enabled) {
goto done;
}
if (g->ops.cg.blcg_ce_load_gating_prod != NULL) {
g->ops.cg.blcg_ce_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
}
void nvgpu_cg_blcg_gr_load_enable(struct gk20a *g)
{
nvgpu_log_fn(g, " ");
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (!g->blcg_enabled) {
goto done;
}
if (g->ops.cg.blcg_gr_load_gating_prod != NULL) {
g->ops.cg.blcg_gr_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
}
void nvgpu_cg_slcg_fb_ltc_load_enable(struct gk20a *g)
{
nvgpu_log_fn(g, " ");
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (!g->slcg_enabled) {
goto done;
}
if (g->ops.cg.slcg_fb_load_gating_prod != NULL) {
g->ops.cg.slcg_fb_load_gating_prod(g, true);
}
if (g->ops.cg.slcg_ltc_load_gating_prod != NULL) {
g->ops.cg.slcg_ltc_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
}
static void nvgpu_cg_slcg_priring_load_prod(struct gk20a *g, bool enable)
{
if (g->ops.cg.slcg_priring_load_gating_prod != NULL) {
g->ops.cg.slcg_priring_load_gating_prod(g, enable);
}
if (g->ops.cg.slcg_rs_ctrl_fbp_load_gating_prod != NULL) {
g->ops.cg.slcg_rs_ctrl_fbp_load_gating_prod(g, enable);
}
if (g->ops.cg.slcg_rs_ctrl_gpc_load_gating_prod != NULL) {
g->ops.cg.slcg_rs_ctrl_gpc_load_gating_prod(g, enable);
}
if (g->ops.cg.slcg_rs_ctrl_sys_load_gating_prod != NULL) {
g->ops.cg.slcg_rs_ctrl_sys_load_gating_prod(g, enable);
}
if (g->ops.cg.slcg_rs_fbp_load_gating_prod != NULL) {
g->ops.cg.slcg_rs_fbp_load_gating_prod(g, enable);
}
if (g->ops.cg.slcg_rs_gpc_load_gating_prod != NULL) {
g->ops.cg.slcg_rs_gpc_load_gating_prod(g, enable);
}
if (g->ops.cg.slcg_rs_sys_load_gating_prod != NULL) {
g->ops.cg.slcg_rs_sys_load_gating_prod(g, enable);
}
}
void nvgpu_cg_slcg_priring_load_enable(struct gk20a *g)
{
nvgpu_log_fn(g, " ");
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (!g->slcg_enabled) {
goto done;
}
nvgpu_cg_slcg_priring_load_prod(g, true);
done:
nvgpu_mutex_release(&g->cg_pg_lock);
}
void nvgpu_cg_slcg_fifo_load_enable(struct gk20a *g)
{
nvgpu_log_fn(g, " ");
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (!g->slcg_enabled) {
goto done;
}
if (g->ops.cg.slcg_fifo_load_gating_prod != NULL) {
g->ops.cg.slcg_fifo_load_gating_prod(g, true);
}
if (g->ops.cg.slcg_runlist_load_gating_prod != NULL) {
g->ops.cg.slcg_runlist_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
}
void nvgpu_cg_slcg_pmu_load_enable(struct gk20a *g)
{
nvgpu_log_fn(g, " ");
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (!g->slcg_enabled) {
goto done;
}
if (g->ops.cg.slcg_pmu_load_gating_prod != NULL) {
g->ops.cg.slcg_pmu_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
}
void nvgpu_cg_slcg_therm_load_enable(struct gk20a *g)
{
nvgpu_log_fn(g, " ");
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (!g->slcg_enabled) {
goto done;
}
if (g->ops.cg.slcg_therm_load_gating_prod != NULL) {
g->ops.cg.slcg_therm_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
}
void nvgpu_cg_slcg_ce2_load_enable(struct gk20a *g)
{
nvgpu_log_fn(g, " ");
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (!g->slcg_enabled) {
goto done;
}
if (g->ops.cg.slcg_ce2_load_gating_prod != NULL) {
g->ops.cg.slcg_ce2_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
}
#if defined(CONFIG_NVGPU_NON_FUSA)
void nvgpu_cg_slcg_timer_load_enable(struct gk20a *g)
{
nvgpu_log_fn(g, " ");
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (!g->slcg_enabled) {
goto done;
}
if (g->ops.cg.slcg_timer_load_gating_prod != NULL) {
g->ops.cg.slcg_timer_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
}
#endif
#ifdef CONFIG_NVGPU_PROFILER
void nvgpu_cg_slcg_perf_load_enable(struct gk20a *g, bool enable)
{
nvgpu_log_fn(g, " ");
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (!g->slcg_enabled) {
goto done;
}
if (g->ops.cg.slcg_perf_load_gating_prod != NULL) {
g->ops.cg.slcg_perf_load_gating_prod(g, enable);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
}
#endif
static void cg_init_gr_slcg_load_gating_prod(struct gk20a *g)
{
if (g->ops.cg.slcg_bus_load_gating_prod != NULL) {
g->ops.cg.slcg_bus_load_gating_prod(g, true);
}
if (g->ops.cg.slcg_chiplet_load_gating_prod != NULL) {
g->ops.cg.slcg_chiplet_load_gating_prod(g, true);
}
if (g->ops.cg.slcg_gr_load_gating_prod != NULL) {
g->ops.cg.slcg_gr_load_gating_prod(g, true);
}
if (g->ops.cg.slcg_perf_load_gating_prod != NULL) {
g->ops.cg.slcg_perf_load_gating_prod(g, true);
}
if (g->ops.cg.slcg_xbar_load_gating_prod != NULL) {
g->ops.cg.slcg_xbar_load_gating_prod(g, true);
}
if (g->ops.cg.slcg_hshub_load_gating_prod != NULL) {
g->ops.cg.slcg_hshub_load_gating_prod(g, true);
}
}
static void cg_init_gr_blcg_load_gating_prod(struct gk20a *g)
{
if (g->ops.cg.blcg_bus_load_gating_prod != NULL) {
g->ops.cg.blcg_bus_load_gating_prod(g, true);
}
if (g->ops.cg.blcg_gr_load_gating_prod != NULL) {
g->ops.cg.blcg_gr_load_gating_prod(g, true);
}
if (g->ops.cg.blcg_xbar_load_gating_prod != NULL) {
g->ops.cg.blcg_xbar_load_gating_prod(g, true);
}
if (g->ops.cg.blcg_hshub_load_gating_prod != NULL) {
g->ops.cg.blcg_hshub_load_gating_prod(g, true);
}
}
void nvgpu_cg_init_gr_load_gating_prod(struct gk20a *g)
{
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, " ");
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (!g->slcg_enabled) {
goto check_can_blcg;
}
cg_init_gr_slcg_load_gating_prod(g);
check_can_blcg:
if (!g->blcg_enabled) {
goto exit;
}
cg_init_gr_blcg_load_gating_prod(g);
exit:
nvgpu_mutex_release(&g->cg_pg_lock);
}
#ifdef CONFIG_NVGPU_NON_FUSA
void nvgpu_cg_elcg_enable(struct gk20a *g)
{
nvgpu_log_fn(g, " ");
g->ops.gr.init.wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (g->elcg_enabled) {
nvgpu_cg_set_mode(g, ELCG_MODE, ELCG_AUTO);
}
nvgpu_mutex_release(&g->cg_pg_lock);
}
void nvgpu_cg_elcg_disable(struct gk20a *g)
{
nvgpu_log_fn(g, " ");
g->ops.gr.init.wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (g->elcg_enabled) {
nvgpu_cg_set_mode(g, ELCG_MODE, ELCG_RUN);
}
nvgpu_mutex_release(&g->cg_pg_lock);
}
void nvgpu_cg_blcg_mode_enable(struct gk20a *g)
{
nvgpu_log_fn(g, " ");
g->ops.gr.init.wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (g->blcg_enabled) {
nvgpu_cg_set_mode(g, BLCG_MODE, BLCG_AUTO);
}
nvgpu_mutex_release(&g->cg_pg_lock);
}
void nvgpu_cg_blcg_mode_disable(struct gk20a *g)
{
nvgpu_log_fn(g, " ");
g->ops.gr.init.wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (g->blcg_enabled) {
nvgpu_cg_set_mode(g, BLCG_MODE, BLCG_RUN);
}
nvgpu_mutex_release(&g->cg_pg_lock);
}
void nvgpu_cg_slcg_gr_perf_ltc_load_enable(struct gk20a *g)
{
nvgpu_log_fn(g, " ");
g->ops.gr.init.wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (!g->slcg_enabled) {
goto done;
}
if (g->ops.cg.slcg_ltc_load_gating_prod != NULL) {
g->ops.cg.slcg_ltc_load_gating_prod(g, true);
}
if (g->ops.cg.slcg_perf_load_gating_prod != NULL) {
g->ops.cg.slcg_perf_load_gating_prod(g, true);
}
if (g->ops.cg.slcg_gr_load_gating_prod != NULL) {
g->ops.cg.slcg_gr_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
}
void nvgpu_cg_slcg_gr_perf_ltc_load_disable(struct gk20a *g)
{
nvgpu_log_fn(g, " ");
g->ops.gr.init.wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (!g->slcg_enabled) {
goto done;
}
if (g->ops.cg.slcg_gr_load_gating_prod != NULL) {
g->ops.cg.slcg_gr_load_gating_prod(g, false);
}
if (g->ops.cg.slcg_perf_load_gating_prod != NULL) {
g->ops.cg.slcg_perf_load_gating_prod(g, false);
}
if (g->ops.cg.slcg_ltc_load_gating_prod != NULL) {
g->ops.cg.slcg_ltc_load_gating_prod(g, false);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
}
void nvgpu_cg_elcg_set_elcg_enabled(struct gk20a *g, bool enable)
{
nvgpu_log_fn(g, " ");
g->ops.gr.init.wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (enable) {
if (!g->elcg_enabled) {
g->elcg_enabled = true;
nvgpu_cg_set_mode(g, ELCG_MODE, ELCG_AUTO);
}
} else {
if (g->elcg_enabled) {
g->elcg_enabled = false;
nvgpu_cg_set_mode(g, ELCG_MODE, ELCG_RUN);
}
}
if (g->ops.cg.elcg_ce_load_gating_prod != NULL) {
g->ops.cg.elcg_ce_load_gating_prod(g, g->elcg_enabled);
}
nvgpu_mutex_release(&g->cg_pg_lock);
}
void nvgpu_cg_blcg_set_blcg_enabled(struct gk20a *g, bool enable)
{
bool load = false;
nvgpu_log_fn(g, " ");
g->ops.gr.init.wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (enable) {
if (!g->blcg_enabled) {
load = true;
g->blcg_enabled = true;
}
} else {
if (g->blcg_enabled) {
load = true;
g->blcg_enabled = false;
}
}
if (!load ) {
goto done;
}
if (g->ops.cg.blcg_bus_load_gating_prod != NULL) {
g->ops.cg.blcg_bus_load_gating_prod(g, enable);
}
if (g->ops.cg.blcg_ce_load_gating_prod != NULL) {
g->ops.cg.blcg_ce_load_gating_prod(g, enable);
}
if (g->ops.cg.blcg_fb_load_gating_prod != NULL) {
g->ops.cg.blcg_fb_load_gating_prod(g, enable);
}
if (g->ops.cg.blcg_fifo_load_gating_prod != NULL) {
g->ops.cg.blcg_fifo_load_gating_prod(g, enable);
}
if (g->ops.cg.blcg_gr_load_gating_prod != NULL) {
g->ops.cg.blcg_gr_load_gating_prod(g, enable);
}
if (g->ops.cg.blcg_runlist_load_gating_prod != NULL) {
g->ops.cg.blcg_runlist_load_gating_prod(g, enable);
}
if (g->ops.cg.blcg_ltc_load_gating_prod != NULL) {
g->ops.cg.blcg_ltc_load_gating_prod(g, enable);
}
if (g->ops.cg.blcg_pmu_load_gating_prod != NULL) {
g->ops.cg.blcg_pmu_load_gating_prod(g, enable);
}
if (g->ops.cg.blcg_xbar_load_gating_prod != NULL) {
g->ops.cg.blcg_xbar_load_gating_prod(g, enable);
}
if (g->ops.cg.blcg_hshub_load_gating_prod != NULL) {
g->ops.cg.blcg_hshub_load_gating_prod(g, enable);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
}
void nvgpu_cg_slcg_set_slcg_enabled(struct gk20a *g, bool enable)
{
bool load = false;
nvgpu_log_fn(g, " ");
g->ops.gr.init.wait_initialized(g);
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (enable) {
if (!g->slcg_enabled) {
load = true;
g->slcg_enabled = true;
}
} else {
if (g->slcg_enabled) {
load = true;
g->slcg_enabled = false;
}
}
if (!load ) {
goto done;
}
if (g->ops.cg.slcg_bus_load_gating_prod != NULL) {
g->ops.cg.slcg_bus_load_gating_prod(g, enable);
}
if (g->ops.cg.slcg_ce2_load_gating_prod != NULL) {
g->ops.cg.slcg_ce2_load_gating_prod(g, enable);
}
if (g->ops.cg.slcg_chiplet_load_gating_prod != NULL) {
g->ops.cg.slcg_chiplet_load_gating_prod(g, enable);
}
if (g->ops.cg.slcg_fb_load_gating_prod != NULL) {
g->ops.cg.slcg_fb_load_gating_prod(g, enable);
}
if (g->ops.cg.slcg_fifo_load_gating_prod != NULL) {
g->ops.cg.slcg_fifo_load_gating_prod(g, enable);
}
if (g->ops.cg.slcg_runlist_load_gating_prod != NULL) {
g->ops.cg.slcg_runlist_load_gating_prod(g, enable);
}
if (g->ops.cg.slcg_timer_load_gating_prod != NULL) {
g->ops.cg.slcg_timer_load_gating_prod(g, enable);
}
if (g->ops.cg.slcg_gr_load_gating_prod != NULL) {
g->ops.cg.slcg_gr_load_gating_prod(g, enable);
}
if (g->ops.cg.slcg_ltc_load_gating_prod != NULL) {
g->ops.cg.slcg_ltc_load_gating_prod(g, enable);
}
if (g->ops.cg.slcg_perf_load_gating_prod != NULL) {
g->ops.cg.slcg_perf_load_gating_prod(g, enable);
}
nvgpu_cg_slcg_priring_load_prod(g, enable);
if (g->ops.cg.slcg_pmu_load_gating_prod != NULL) {
g->ops.cg.slcg_pmu_load_gating_prod(g, enable);
}
if (g->ops.cg.slcg_xbar_load_gating_prod != NULL) {
g->ops.cg.slcg_xbar_load_gating_prod(g, enable);
}
if (g->ops.cg.slcg_hshub_load_gating_prod != NULL) {
g->ops.cg.slcg_hshub_load_gating_prod(g, enable);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
}
void nvgpu_cg_elcg_ce_load_enable(struct gk20a *g)
{
nvgpu_log_fn(g, " ");
nvgpu_mutex_acquire(&g->cg_pg_lock);
if (!g->elcg_enabled) {
goto done;
}
if (g->ops.cg.elcg_ce_load_gating_prod != NULL) {
g->ops.cg.elcg_ce_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
}
#endif
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