mirror of
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Preparing to push hvrtos gpu server changes which requires bellow CFLAGS:
-Werror -Wall -Wextra \
-Wmissing-braces -Wpointer-arith -Wundef \
-Wconversion -Wsign-conversion \
-Wformat-security \
-Wmissing-declarations -Wredundant-decls -Wimplicit-fallthrough
Jira GVSCI-11640
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I25167f17f231ed741f19af87ca0aa72991563a0f
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2653746
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
342 lines
7.8 KiB
C
342 lines
7.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* GSP Test Functions
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*
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* Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <nvgpu/firmware.h>
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#include <nvgpu/falcon.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/log.h>
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#include <nvgpu/gsp.h>
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#include <nvgpu/gsp/gsp_test.h>
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#include "gsp_test.h"
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u32 nvgpu_gsp_get_current_iteration(struct gk20a *g)
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{
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u32 data = 0;
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struct nvgpu_gsp *gsp = g->gsp_stest->gsp;
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nvgpu_log_fn(g, " ");
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data = nvgpu_falcon_mailbox_read(gsp->gsp_flcn, FALCON_MAILBOX_1);
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return data;
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}
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u32 nvgpu_gsp_get_current_test(struct gk20a *g)
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{
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u32 data = 0;
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struct nvgpu_gsp *gsp = g->gsp_stest->gsp;
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nvgpu_log_fn(g, " ");
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data = nvgpu_falcon_mailbox_read(gsp->gsp_flcn, FALCON_MAILBOX_0);
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return data;
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}
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bool nvgpu_gsp_get_test_fail_status(struct gk20a *g)
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{
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struct nvgpu_gsp_test *gsp_stest = g->gsp_stest;
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return gsp_stest->gsp_test.stress_test_fail_status;
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}
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bool nvgpu_gsp_get_stress_test_start(struct gk20a *g)
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{
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struct nvgpu_gsp_test *gsp_stest = g->gsp_stest;
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return gsp_stest->gsp_test.enable_stress_test;
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}
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bool nvgpu_gsp_get_stress_test_load(struct gk20a *g)
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{
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struct nvgpu_gsp_test *gsp_stest = g->gsp_stest;
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if (gsp_stest == NULL)
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return false;
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return gsp_stest->gsp_test.load_stress_test;
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}
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void nvgpu_gsp_set_test_fail_status(struct gk20a *g, bool val)
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{
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struct nvgpu_gsp_test *gsp_stest = g->gsp_stest;
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gsp_stest->gsp_test.stress_test_fail_status = val;
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}
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int nvgpu_gsp_set_stress_test_start(struct gk20a *g, bool flag)
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{
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int err = 0;
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struct nvgpu_gsp *gsp = g->gsp_stest->gsp;
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struct nvgpu_gsp_test *gsp_stest = g->gsp_stest;
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nvgpu_log_fn(g, " ");
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if (flag) {
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nvgpu_info(g, "Enabling GSP test");
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nvgpu_falcon_mailbox_write(gsp->gsp_flcn, FALCON_MAILBOX_1, 0xFFFFFFFF);
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} else {
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nvgpu_info(g, "Halting GSP test");
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nvgpu_gsp_stress_test_halt(g, false);
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}
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gsp_stest->gsp_test.enable_stress_test = flag;
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return err;
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}
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int nvgpu_gsp_set_stress_test_load(struct gk20a *g, bool flag)
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{
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int err = 0;
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nvgpu_log_fn(g, " ");
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if (flag)
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err = nvgpu_gsp_stress_test_bootstrap(g, flag);
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return err;
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}
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static void gsp_test_get_file_names(struct gk20a *g, struct gsp_fw *gsp_ucode)
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{
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/*
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* TODO Switch to GSP specific register
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*/
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if (g->ops.pmu.is_debug_mode_enabled(g)) {
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gsp_ucode->code_name = GSPDBG_RISCV_STRESS_TEST_FW_CODE;
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gsp_ucode->data_name = GSPDBG_RISCV_STRESS_TEST_FW_DATA;
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gsp_ucode->manifest_name = GSPDBG_RISCV_STRESS_TEST_FW_MANIFEST;
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} else {
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gsp_ucode->code_name = GSPPROD_RISCV_STRESS_TEST_FW_CODE;
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gsp_ucode->data_name = GSPPROD_RISCV_STRESS_TEST_FW_DATA;
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gsp_ucode->manifest_name = GSPPROD_RISCV_STRESS_TEST_FW_MANIFEST;
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}
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}
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void nvgpu_gsp_write_test_sysmem_addr(struct gk20a *g)
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{
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struct nvgpu_gsp *gsp = g->gsp_stest->gsp;
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struct nvgpu_falcon *flcn;
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u64 sysmem_addr;
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struct nvgpu_gsp_test *gsp_stest;
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flcn = gsp->gsp_flcn;
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gsp_stest = g->gsp_stest;
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sysmem_addr = nvgpu_mem_get_addr(g, &gsp_stest->gsp_test.gsp_test_sysmem_block);
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nvgpu_falcon_mailbox_write(flcn, FALCON_MAILBOX_0, u64_lo32(sysmem_addr));
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nvgpu_falcon_mailbox_write(flcn, FALCON_MAILBOX_1, u64_hi32(sysmem_addr));
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}
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int nvgpu_gsp_stress_test_bootstrap(struct gk20a *g, bool start)
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{
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int err = 0;
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struct nvgpu_gsp *gsp = g->gsp_stest->gsp;
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struct nvgpu_gsp_test *gsp_stest = g->gsp_stest;
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nvgpu_log_fn(g, " ");
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if (gsp_stest == NULL) {
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nvgpu_err(g, "GSP not initialized");
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err = -EFAULT;
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goto exit;
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}
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if (!start && !(gsp_stest->gsp_test.load_stress_test))
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return err;
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if (start) {
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err = nvgpu_dma_alloc_flags_sys(g,
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NVGPU_DMA_PHYSICALLY_ADDRESSED,
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SZ_64K,
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&g->gsp_stest->gsp_test.gsp_test_sysmem_block);
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if (err != 0) {
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nvgpu_err(g, "GSP test memory alloc failed");
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goto exit;
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}
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}
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gsp_stest->gsp_test.load_stress_test = true;
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#ifdef CONFIG_NVGPU_FALCON_DEBUG
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err = nvgpu_gsp_debug_buf_init(g, GSP_TEST_DEBUG_BUFFER_QUEUE,
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GSP_TEST_DMESG_BUFFER_SIZE);
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if (err != 0) {
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nvgpu_err(g, "GSP sched debug buf init failed");
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goto exit;
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}
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#endif
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gsp_test_get_file_names(g, &gsp->gsp_ucode);
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err = nvgpu_gsp_bootstrap_ns(g, gsp);
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if (err != 0) {
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nvgpu_err(g, "GSP bootstrap failed for stress test");
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goto exit;
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}
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/* wait for mailbox-0 update with non-zero value */
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err = nvgpu_gsp_wait_for_mailbox_update(gsp, 0x0,
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GSP_STRESS_TEST_MAILBOX_PASS, GSP_WAIT_TIME_MS);
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if (err != 0) {
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nvgpu_err(g, "gsp ucode failed to update mailbox-0");
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}
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if (gsp_stest->gsp_test.enable_stress_test) {
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nvgpu_info(g, "Restarting GSP stress test");
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nvgpu_falcon_mailbox_write(gsp->gsp_flcn, FALCON_MAILBOX_1, 0xFFFFFFFF);
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}
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return err;
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exit:
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gsp_stest->gsp_test.load_stress_test = false;
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return err;
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}
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int nvgpu_gsp_stress_test_halt(struct gk20a *g, bool restart)
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{
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int err = 0;
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struct nvgpu_gsp *gsp = g->gsp_stest->gsp;
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struct nvgpu_gsp_test *gsp_stest = g->gsp_stest;
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nvgpu_log_fn(g, " ");
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if (gsp == NULL) {
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nvgpu_info(g, "GSP not initialized");
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goto exit;
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}
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nvgpu_gsp_suspend(g, gsp);
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if (restart && (gsp_stest->gsp_test.load_stress_test == false)) {
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nvgpu_info(g, "GSP stress test not loaded ");
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goto exit;
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}
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err = nvgpu_falcon_reset(gsp->gsp_flcn);
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if (err != 0) {
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nvgpu_err(g, "gsp reset failed err=%d", err);
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goto exit;
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}
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if (!restart) {
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gsp_stest->gsp_test.load_stress_test = false;
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nvgpu_dma_free(g, &gsp_stest->gsp_test.gsp_test_sysmem_block);
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}
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exit:
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return err;
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}
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bool nvgpu_gsp_is_stress_test(struct gk20a *g)
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{
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if (g->gsp_stest->gsp_test.load_stress_test)
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return true;
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else
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return false;
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}
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static void gsp_test_sw_deinit(struct gk20a *g, struct nvgpu_gsp_test *gsp_stest)
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{
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nvgpu_dma_free(g, &gsp_stest->gsp_test.gsp_test_sysmem_block);
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nvgpu_kfree(g, gsp_stest);
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gsp_stest = NULL;
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}
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void nvgpu_gsp_test_sw_deinit(struct gk20a *g)
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{
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struct nvgpu_gsp_test *gsp_stest = g->gsp_stest;
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nvgpu_log_fn(g, " ");
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if (gsp_stest == NULL) {
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nvgpu_info(g, "GSP stest not initialized");
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return;
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}
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if (gsp_stest->gsp != NULL) {
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nvgpu_gsp_sw_deinit(g, gsp_stest->gsp);
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}
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if (gsp_stest != NULL) {
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gsp_test_sw_deinit(g, gsp_stest);
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}
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}
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int nvgpu_gsp_stress_test_sw_init(struct gk20a *g)
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{
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int err = 0;
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struct nvgpu_gsp *gsp;
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nvgpu_log_fn(g, " ");
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if (g->gsp_stest != NULL) {
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/*
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* Recovery/unrailgate case, we do not need to do gsp_stest init as
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* gsp_stest is set during cold boot & doesn't execute gsp_stest clean
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* up as part of power off sequence, so reuse to perform faster boot.
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*/
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nvgpu_gsp_stress_test_bootstrap(g, false);
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return err;
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}
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/* Init struct holding the gsp_stest software state */
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g->gsp_stest = (struct nvgpu_gsp_test *)
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nvgpu_kzalloc(g, sizeof(struct nvgpu_gsp_test));
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if (g->gsp_stest == NULL) {
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err = -ENOMEM;
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goto de_init;
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}
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/* Init struct holding the gsp software state */
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g->gsp_stest->gsp = (struct nvgpu_gsp *)
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nvgpu_kzalloc(g, sizeof(struct nvgpu_gsp));
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if (g->gsp_stest->gsp == NULL) {
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err = -ENOMEM;
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goto de_init;
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}
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gsp = g->gsp_stest->gsp;
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/* gsp falcon software state */
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gsp->gsp_flcn = &g->gsp_flcn;
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gsp->g = g;
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/* Init isr mutex */
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nvgpu_mutex_init(&gsp->isr_mutex);
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nvgpu_log_fn(g, " Done ");
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return err;
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de_init:
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nvgpu_gsp_test_sw_deinit(g);
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return err;
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}
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void nvgpu_gsp_stest_isr(struct gk20a *g)
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{
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struct nvgpu_gsp *gsp = g->gsp_stest->gsp;
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g->ops.gsp.gsp_isr(g, gsp);
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}
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