mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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3e43f92f21
Mass copy ga10b & ga100 sources from nvgpu-next repo. TOP COMMIT-ID: 98f530e6924c844a1bf46816933a7fe015f3cce1 Jira NVGPU-4771 Change-Id: Ibf7102e9208133f8ef3bd3a98381138d5396d831 Signed-off-by: Sagar Kadamati <skadamati@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2524817 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
80 lines
3.1 KiB
C
80 lines
3.1 KiB
C
/*
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/device.h>
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#include <nvgpu/engines.h>
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#include <nvgpu/runlist.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/fifo.h>
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int nvgpu_next_engine_init_one_dev(struct gk20a *g,
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const struct nvgpu_device *dev)
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{
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struct nvgpu_device *dev_rw = (struct nvgpu_device *)dev;
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/*
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* Currently due to the nature of the nvgpu_next repo, this will still
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* be called even on non-ga10b systems. Eventually this code will fold into
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* the nvgpu-linux repo, at which point this logic will be present in
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* nvgpu_engine_init_one_dev().
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*
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* In any event, the purpose of this is to make sure we _don't_ execute
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* this code pre-ga10b. We can check for HALs that only exist on ga10x to
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* short circuit.
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*/
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if (g->ops.runlist.get_engine_id_from_rleng_id == NULL) {
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return 0;
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}
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/*
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* Init PBDMA info for this device; needs FIFO to be alive to do this.
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* SW expects at least pbdma instance0 to be valid.
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*
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* See JIRA NVGPU-4980 for multiple pbdma support.
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*/
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g->ops.runlist.get_pbdma_info(g,
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dev->next.rl_pri_base,
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&dev_rw->next.pbdma_info);
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if (dev->next.pbdma_info.pbdma_id[ENGINE_PBDMA_INSTANCE0] ==
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NVGPU_INVALID_PBDMA_ID) {
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nvgpu_err(g, "busted pbdma info: no pbdma for engine id:%d",
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dev->engine_id);
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return -EINVAL;
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}
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dev_rw->pbdma_id = dev->next.pbdma_info.pbdma_id[ENGINE_PBDMA_INSTANCE0];
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nvgpu_log(g, gpu_dbg_device, "Parsed engine: ID: %u", dev->engine_id);
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nvgpu_log(g, gpu_dbg_device, " inst_id %u, runlist_id: %u, fault id %u",
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dev->inst_id, dev->runlist_id, dev->fault_id);
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nvgpu_log(g, gpu_dbg_device, " intr_id %u, reset_id %u",
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dev->intr_id, dev->reset_id);
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nvgpu_log(g, gpu_dbg_device, " engine_type %u",
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dev->type);
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nvgpu_log(g, gpu_dbg_device, " reset_id 0x%08x, rleng_id 0x%x",
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dev->reset_id, dev->next.rleng_id);
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nvgpu_log(g, gpu_dbg_device, " runlist_pri_base 0x%x",
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dev->next.rl_pri_base);
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return 0;
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}
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