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3e43f92f21
Mass copy ga10b & ga100 sources from nvgpu-next repo. TOP COMMIT-ID: 98f530e6924c844a1bf46816933a7fe015f3cce1 Jira NVGPU-4771 Change-Id: Ibf7102e9208133f8ef3bd3a98381138d5396d831 Signed-off-by: Sagar Kadamati <skadamati@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2524817 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
86 lines
3.0 KiB
C
86 lines
3.0 KiB
C
/*
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/log2.h>
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#include <nvgpu/utils.h>
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#include <nvgpu/io.h>
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#include <nvgpu/bitops.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/debug.h>
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#include <nvgpu/fifo.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/pbdma_status.h>
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#include <nvgpu/hw/ga10b/hw_pbdma_ga10b.h>
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#include "pbdma_ga10b.h"
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void ga10b_pbdma_dump_status(struct gk20a *g, struct nvgpu_debug_context *o)
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{
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u32 i, host_num_pbdma;
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struct nvgpu_pbdma_status_info pbdma_status;
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host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
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gk20a_debug_output(o, "PBDMA Status - chip %-5s", g->name);
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gk20a_debug_output(o, "-------------------------");
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for (i = 0U; i < host_num_pbdma; i++) {
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g->ops.pbdma_status.read_pbdma_status_info(g, i,
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&pbdma_status);
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gk20a_debug_output(o, "pbdma %d:", i);
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gk20a_debug_output(o,
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" id: %d - %-9s next_id: - %d %-9s | status: %s",
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pbdma_status.id,
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nvgpu_pbdma_status_is_id_type_tsg(&pbdma_status) ?
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"[tsg]" : "[channel]",
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pbdma_status.next_id,
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nvgpu_pbdma_status_is_next_id_type_tsg(
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&pbdma_status) ?
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"[tsg]" : "[channel]",
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nvgpu_fifo_decode_pbdma_ch_eng_status(
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pbdma_status.pbdma_channel_status));
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gk20a_debug_output(o,
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" PBDMA_PUT %016llx PBDMA_GET %016llx",
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(u64)nvgpu_readl(g, pbdma_put_r(i)) +
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((u64)nvgpu_readl(g, pbdma_put_hi_r(i)) << 32ULL),
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(u64)nvgpu_readl(g, pbdma_get_r(i)) +
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((u64)nvgpu_readl(g, pbdma_get_hi_r(i)) << 32ULL));
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gk20a_debug_output(o,
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" GP_PUT %08x GP_GET %08x "
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"FETCH %08x HEADER %08x",
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nvgpu_readl(g, pbdma_gp_put_r(i)),
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nvgpu_readl(g, pbdma_gp_get_r(i)),
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nvgpu_readl(g, pbdma_gp_fetch_r(i)),
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nvgpu_readl(g, pbdma_pb_header_r(i)));
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gk20a_debug_output(o,
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" HDR %08x SHADOW0 %08x SHADOW1 %08x",
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g->ops.pbdma.read_data(g, i),
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nvgpu_readl(g, pbdma_gp_shadow_0_r(i)),
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nvgpu_readl(g, pbdma_gp_shadow_1_r(i)));
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}
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gk20a_debug_output(o, " ");
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}
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