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3fe70bf86e
Below CE interrupts do not have any users(usecases) on safety build;
disable them only on safety build.
1. BLOCKPIPE stall intr: Not used by GFX(VKSC) and CUDA on safety.
2. NONBLOCK_PIPE nonstall intr: Non-stall intrs are not supported
on safety build. Also, this one is not used by GFX(VKSC)
and CUDA.
3. STALLING_DEBUG intr: Added in Orin tree. It is only needed for
debugging. Disable on safety build as there is no current
usage in driver.
4. POISON_ERROR intr: Poison is a fault containment and not
supported on GA10b.
5. INVALID_CONFIG intr: Floor sweeping not supported on functional
safety SKU.
Bug 3548082
Change-Id: I8d97ccb38f138b2c04a780e1c255a64d28723405
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2671927
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
86 lines
2.7 KiB
C
86 lines
2.7 KiB
C
/*
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* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/types.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/engines.h>
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#include <nvgpu/device.h>
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#include <nvgpu/ce.h>
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#include <nvgpu/power_features/cg.h>
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#include <nvgpu/cic_mon.h>
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#include <nvgpu/mc.h>
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int nvgpu_ce_init_support(struct gk20a *g)
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{
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int err = 0;
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if (g->ops.ce.set_pce2lce_mapping != NULL) {
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g->ops.ce.set_pce2lce_mapping(g);
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}
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/*
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* Bug 1895019
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* Each time PCE2LCE config is updated and if it happens to
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* map a LCE which was previously unmapped, then ELCG would have turned
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* off the clock to the unmapped LCE and when the LCE config is updated,
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* a race occurs between the config update and ELCG turning on the clock
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* to that LCE, this might result in LCE dropping the config update.
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* To avoid such a race, each time PCE2LCE config is updated toggle
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* resets for all LCEs.
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*/
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err = nvgpu_mc_reset_devtype(g, NVGPU_DEVTYPE_LCE);
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if (err != 0) {
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nvgpu_err(g, "NVGPU_DEVTYPE_LCE reset failed");
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return err;
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}
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nvgpu_cg_slcg_ce2_load_enable(g);
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nvgpu_cg_blcg_ce_load_enable(g);
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#if defined(CONFIG_NVGPU_NON_FUSA)
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nvgpu_cg_elcg_ce_load_enable(g);
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#endif
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if (g->ops.ce.init_prod_values != NULL) {
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g->ops.ce.init_prod_values(g);
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}
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#ifdef CONFIG_NVGPU_NONSTALL_INTR
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if (g->ops.ce.init_hw != NULL) {
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g->ops.ce.init_hw(g);
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}
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#endif
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if (g->ops.ce.intr_enable != NULL) {
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g->ops.ce.intr_enable(g, true);
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}
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/** Enable interrupts at MC level */
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nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_CE, NVGPU_CIC_INTR_ENABLE);
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#ifdef CONFIG_NVGPU_NONSTALL_INTR
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nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_CE, NVGPU_CIC_INTR_ENABLE);
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#endif
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return 0;
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}
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