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ee4970a33f
Drastically simplify and move the aligment computation for buffers getting mapped into the SGT code. An SGT is all that is needed for computing the alignment. However, this did require that a new SGT op was added: nvgpu_sgt_iommuable() This function returns true if the passed SGT is IOMMU'able and must be implemented by an SGT implementation that has IOMMU'able buffers. If this function is left as NULL then it is assumed that the buffer is not IOMMU'able. Also cleanup the parameter ordering convention among all nvgpu_sgt functions. Previously there was a mishmash of different parameter orderings. This patch now standardizes on the gk20a first approach seen everywhere else in the driver. JIRA NVGPU-30 JIRA NVGPU-246 JIRA NVGPU-71 Change-Id: Ic4ab7b752847cf795c7cfafed5a07818217bba86 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1583985 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
120 lines
3.6 KiB
C
120 lines
3.6 KiB
C
/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/kmem.h>
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/vidmem.h>
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#include "gk20a/gk20a.h"
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void *nvgpu_sgt_get_next(struct nvgpu_sgt *sgt, void *sgl)
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{
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return sgt->ops->sgl_next(sgl);
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}
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u64 nvgpu_sgt_get_phys(struct nvgpu_sgt *sgt, void *sgl)
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{
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return sgt->ops->sgl_phys(sgl);
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}
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u64 nvgpu_sgt_get_dma(struct nvgpu_sgt *sgt, void *sgl)
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{
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return sgt->ops->sgl_dma(sgl);
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}
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u64 nvgpu_sgt_get_length(struct nvgpu_sgt *sgt, void *sgl)
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{
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return sgt->ops->sgl_length(sgl);
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}
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u64 nvgpu_sgt_get_gpu_addr(struct gk20a *g, struct nvgpu_sgt *sgt, void *sgl,
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struct nvgpu_gmmu_attrs *attrs)
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{
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return sgt->ops->sgl_gpu_addr(g, sgl, attrs);
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}
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bool nvgpu_sgt_iommuable(struct gk20a *g, struct nvgpu_sgt *sgt)
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{
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if (sgt->ops->sgt_iommuable)
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return sgt->ops->sgt_iommuable(g, sgt);
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return false;
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}
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void nvgpu_sgt_free(struct gk20a *g, struct nvgpu_sgt *sgt)
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{
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if (sgt && sgt->ops->sgt_free)
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sgt->ops->sgt_free(g, sgt);
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}
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u64 nvgpu_mem_iommu_translate(struct gk20a *g, u64 phys)
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{
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/* ensure it is not vidmem allocation */
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WARN_ON(nvgpu_addr_is_vidmem_page_alloc(phys));
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if (nvgpu_iommuable(g) && g->ops.mm.get_iommu_bit)
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return phys | 1ULL << g->ops.mm.get_iommu_bit(g);
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return phys;
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}
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/*
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* Determine alignment for a passed buffer. Necessary since the buffer may
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* appear big enough to map with large pages but the SGL may have chunks that
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* are not aligned on a 64/128kB large page boundary. There's also the
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* possibility chunks are odd sizes which will necessitate small page mappings
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* to correctly glue them together into a contiguous virtual mapping.
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*/
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u64 nvgpu_sgt_alignment(struct gk20a *g, struct nvgpu_sgt *sgt)
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{
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u64 align = 0, chunk_align = 0;
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void *sgl;
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/*
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* If this SGT is iommuable and we want to use the IOMMU address then
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* the SGT's first entry has the IOMMU address. We will align on this
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* and double check length of buffer later. Also, since there's an
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* IOMMU we know that this DMA address is contiguous.
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*/
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if (!g->mm.bypass_smmu &&
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nvgpu_sgt_iommuable(g, sgt) &&
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nvgpu_sgt_get_dma(sgt, sgt->sgl))
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return 1ULL << __ffs(nvgpu_sgt_get_dma(sgt, sgt->sgl));
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/*
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* Otherwise the buffer is not iommuable (VIDMEM, for example) or we are
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* bypassing the IOMMU and need to use the underlying physical entries
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* of the SGT.
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*/
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nvgpu_sgt_for_each_sgl(sgl, sgt) {
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chunk_align = 1ULL << __ffs(nvgpu_sgt_get_phys(sgt, sgl) |
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nvgpu_sgt_get_length(sgt, sgl));
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if (align)
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align = min(align, chunk_align);
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else
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align = chunk_align;
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}
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return align;
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}
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