Seema Khowala 40d2f60903 gpu: nvgpu: gv11b: implement init_pbdma_intr_desc fifo ops ...

Init device_fatal, channel_fatal and restartable fifo intr pbdma s/w
variables for pbdma_intr_0 interrupt masks.

pbdma_intr_0 field changes for gv11b:-
bit 8(lbreq) does not exists in hw.
bit 28 (syncpoint_illegal)is removed in hw.
bit 20 is reused for clear_faulted_error in hw.
bit 24 (eng_reset) and bit 25 (semaphore) always existed in hw
but never handled in s/w. These are added as channel fatal.

JIRA GPUT19X-47

Change-Id: I13673430408f1cf7ef762075a29b94196f79a349
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1325401
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

2017-03-23 09:34:13 -07:00

..

nvgpu

gpu: nvgpu: gv11b: implement init_pbdma_intr_desc fifo ops

2017-03-23 09:34:13 -07:00