Files
linux-nvgpu/drivers/gpu/nvgpu/common/ce/ce.c
Antony Clince Alex cce1d7ad84 gpu: nvgpu: update device management framework to remove unusable engines
On certain platforms, not all copy engine instances are usable. The user
shouldn't submit any work to these engines. To enforce this, remove
these engines from active/host_engine list, this should ensure that these
engines do not get advertised to userspace. In order to accomplish this
introduce the following functions:
- nvgpu_engine_remove_one_dev: This function removes the specified device
  entry from following device lists: fifo->host_engines, fifo->active_engines,
  runlist->rl_dev_list, runlist->eng_bitmask.

Replace iteration over LCE device type entries using
nvgpu_device_for_each(g, dev, NVGPU_DEVTYPE_LCE), along with this introduce
macro nvgpu_device_for_each_safe.

Introduce gpu_dbg_ce flag for CE debugging.

Bug 3370462

Change-Id: I2e21f18363c6e53630d129da241c8fece106cd33
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2616711
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-11-18 09:18:55 -08:00

82 lines
2.7 KiB
C

/*
* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/types.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/engines.h>
#include <nvgpu/device.h>
#include <nvgpu/ce.h>
#include <nvgpu/power_features/cg.h>
#include <nvgpu/cic_mon.h>
#include <nvgpu/mc.h>
int nvgpu_ce_init_support(struct gk20a *g)
{
int err = 0;
if (g->ops.ce.set_pce2lce_mapping != NULL) {
g->ops.ce.set_pce2lce_mapping(g);
}
/*
* Bug 1895019
* Each time PCE2LCE config is updated and if it happens to
* map a LCE which was previously unmapped, then ELCG would have turned
* off the clock to the unmapped LCE and when the LCE config is updated,
* a race occurs between the config update and ELCG turning on the clock
* to that LCE, this might result in LCE dropping the config update.
* To avoid such a race, each time PCE2LCE config is updated toggle
* resets for all LCEs.
*/
err = nvgpu_mc_reset_devtype(g, NVGPU_DEVTYPE_LCE);
if (err != 0) {
nvgpu_err(g, "NVGPU_DEVTYPE_LCE reset failed");
return err;
}
nvgpu_cg_slcg_ce2_load_enable(g);
nvgpu_cg_blcg_ce_load_enable(g);
#if defined(CONFIG_NVGPU_NON_FUSA)
nvgpu_cg_elcg_ce_load_enable(g);
#endif
if (g->ops.ce.init_prod_values != NULL) {
g->ops.ce.init_prod_values(g);
}
if (g->ops.ce.init_hw != NULL) {
g->ops.ce.init_hw(g);
}
if (g->ops.ce.intr_enable != NULL) {
g->ops.ce.intr_enable(g, true);
}
/** Enable interrupts at MC level */
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_CE, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_CE, NVGPU_CIC_INTR_ENABLE);
return 0;
}