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8c455dff18
implemented sequence support which is needed for cmd/msg for sequencing all the commands sent from NVGPU to gsp and also to handle cmd responses with respect to correspondind assigned sequences. NVGPU-6784 Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com> Change-Id: I7d0bb015227c11512ec3c7a5ef7117e149704206 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2590607 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
75 lines
2.5 KiB
C
75 lines
2.5 KiB
C
/*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GSP_SEQ_H
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#define NVGPU_GSP_SEQ_H
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#include <nvgpu/types.h>
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#include <nvgpu/lock.h>
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struct gk20a;
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struct nv_flcn_msg_gsp;
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#define GSP_MAX_NUM_SEQUENCES 256U
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#define GSP_SEQ_BIT_SHIFT 5U
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#define GSP_SEQ_TBL_SIZE (GSP_MAX_NUM_SEQUENCES >> GSP_SEQ_BIT_SHIFT)
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enum gsp_seq_state {
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GSP_SEQ_STATE_FREE = 0U,
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GSP_SEQ_STATE_PENDING,
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GSP_SEQ_STATE_USED
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};
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typedef void (*gsp_callback)(struct gk20a *g, struct nv_flcn_msg_gsp *msg,
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void *param, u32 status);
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struct gsp_sequence {
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u8 id;
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enum gsp_seq_state state;
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u8 *out_payload;
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gsp_callback callback;
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void *cb_params;
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};
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struct gsp_sequences {
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struct gsp_sequence *seq;
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unsigned long gsp_seq_tbl[GSP_SEQ_TBL_SIZE];
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struct nvgpu_mutex gsp_seq_lock;
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};
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int nvgpu_gsp_sequences_init(struct gk20a *g, struct nvgpu_gsp *gsp);
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void nvgpu_gsp_sequences_free(struct gk20a *g,
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struct gsp_sequences *sequences);
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int nvgpu_gsp_seq_acquire(struct gk20a *g,
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struct gsp_sequences *sequences,
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struct gsp_sequence **pseq,
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gsp_callback callback, void *cb_params);
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int nvgpu_gsp_seq_response_handle(struct gk20a *g,
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struct gsp_sequences *sequences,
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struct nv_flcn_msg_gsp *msg, u32 seq_id);
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u8 nvgpu_gsp_seq_get_id(struct gsp_sequence *seq);
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void nvgpu_gsp_seq_set_state(struct gsp_sequence *seq,
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enum gsp_seq_state state);
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void gsp_seq_release(struct gsp_sequences *sequences,
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struct gsp_sequence *seq);
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#endif /* NVGPU_GSP_SEQ_H */
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