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4277f65834
Advisory Rule 2.7 states that there should be no unused parameters in functions. This patch removes unused function parameters from the following: * nvgpu_channel_ctxsw_timeout_debug_dump_state() * nvgpu_channel_destroy() * nvgpu_tsg_destroy() * nvgpu_rc_pdbma_fault() Jira NVGPU-3178 Change-Id: I12ad0d287fd7980533663a9776428ef5d4fd1fb9 Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2176066 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
68 lines
2.5 KiB
C
68 lines
2.5 KiB
C
/*
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* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_RC_H
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#define NVGPU_RC_H
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#include <nvgpu/types.h>
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#define RC_TYPE_NO_RC 0U
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#define RC_TYPE_MMU_FAULT 1U
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#define RC_TYPE_PBDMA_FAULT 2U
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#define RC_TYPE_GR_FAULT 3U
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#define RC_TYPE_PREEMPT_TIMEOUT 4U
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#define RC_TYPE_CTXSW_TIMEOUT 5U
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#define RC_TYPE_RUNLIST_UPDATE_TIMEOUT 6U
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#define RC_TYPE_FORCE_RESET 7U
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#define RC_TYPE_SCHED_ERR 8U
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#define INVAL_ID (~U32(0U))
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struct gk20a;
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struct nvgpu_fifo;
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struct nvgpu_tsg;
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struct nvgpu_channel;
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struct nvgpu_pbdma_status_info;
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void nvgpu_rc_ctxsw_timeout(struct gk20a *g, u32 eng_bitmask,
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struct nvgpu_tsg *tsg, bool debug_dump);
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void nvgpu_rc_pbdma_fault(struct gk20a *g, u32 pbdma_id, u32 error_notifier,
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struct nvgpu_pbdma_status_info *pbdma_status);
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void nvgpu_rc_runlist_update(struct gk20a *g, u32 runlist_id);
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void nvgpu_rc_preempt_timeout(struct gk20a *g, struct nvgpu_tsg *tsg);
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void nvgpu_rc_gr_fault(struct gk20a *g,
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struct nvgpu_tsg *tsg, struct nvgpu_channel *ch);
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void nvgpu_rc_sched_error_bad_tsg(struct gk20a *g);
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void nvgpu_rc_tsg_and_related_engines(struct gk20a *g, struct nvgpu_tsg *tsg,
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bool debug_dump, u32 rc_type);
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void nvgpu_rc_fifo_recover(struct gk20a *g,
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u32 eng_bitmask, /* if zero, will be queried from HW */
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u32 hw_id, /* if ~0, will be queried from HW */
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bool id_is_tsg, /* ignored if hw_id == ~0 */
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bool id_is_known, bool debug_dump, u32 rc_type);
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#endif /* NVGPU_RC_H */
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