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df4e88a21d
In t19x, gv11b semaphore read and write operations are translated to host1x syncpoint read and write operations using semaphore syncpoint shim aperture. Implement relevant vgpu hal functions for this in fifo hal. Jira EVLR-1571 Change-Id: I6296cc6e592ea991e1c01bc9662d02fb063ff3c7 Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1516367 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
47 lines
1.2 KiB
C
47 lines
1.2 KiB
C
/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __TEGRA_VGPU_T19X_H
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#define __TEGRA_VGPU_T19X_H
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#define TEGRA_VGPU_CMD_ALLOC_CTX_HEADER 100
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#define TEGRA_VGPU_CMD_FREE_CTX_HEADER 101
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#define TEGRA_VGPU_CMD_MAP_SYNCPT 102
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struct tegra_vgpu_alloc_ctx_header_params {
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u64 ch_handle;
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u64 ctx_header_va;
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};
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struct tegra_vgpu_free_ctx_header_params {
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u64 ch_handle;
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};
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struct tegra_vgpu_map_syncpt_params {
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u64 as_handle;
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u64 gpu_va;
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u64 len;
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u64 offset;
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u8 prot;
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};
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union tegra_vgpu_t19x_params {
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struct tegra_vgpu_alloc_ctx_header_params alloc_ctx_header;
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struct tegra_vgpu_free_ctx_header_params free_ctx_header;
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struct tegra_vgpu_map_syncpt_params map_syncpt;
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};
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#define TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT 100
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#endif
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