mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 18:16:01 +03:00
1da69dd8b2
Remove the mm.get_iova_addr() HAL and replace it with a new HAL called mm.gpu_phys_addr(). This new HAL provides the real phys address that should be passed to the GPU from a physical address obtained from a scatter list. It also provides a mechanism by which the HAL code can add extra bits to a GPU physical address based on the attributes passed in. This is necessary during GMMU page table programming. Also remove the flags argument from the various address functions. This flag was used for adding an IO coherence bit to the GPU physical address which is not supported. JIRA NVGPU-30 Change-Id: I69af5b1c6bd905c4077c26c098fac101c6b41a33 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1530864 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
114 lines
2.9 KiB
C
114 lines
2.9 KiB
C
/*
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* GK20A memory interface
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*
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* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <trace/events/gk20a.h>
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#include "gk20a.h"
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#include "kind_gk20a.h"
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#include "fb_gk20a.h"
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#include <nvgpu/timers.h>
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#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
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#include <nvgpu/hw/gk20a/hw_fb_gk20a.h>
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void fb_gk20a_reset(struct gk20a *g)
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{
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u32 val;
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gk20a_dbg_info("reset gk20a fb");
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g->ops.mc.reset(g, mc_enable_pfb_enabled_f() |
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mc_enable_l2_enabled_f() |
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mc_enable_xbar_enabled_f() |
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mc_enable_hub_enabled_f());
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val = gk20a_readl(g, mc_elpg_enable_r());
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val |= mc_elpg_enable_xbar_enabled_f()
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| mc_elpg_enable_pfb_enabled_f()
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| mc_elpg_enable_hub_enabled_f();
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gk20a_writel(g, mc_elpg_enable_r(), val);
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}
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void gk20a_fb_init_hw(struct gk20a *g)
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{
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u32 addr = nvgpu_mem_get_addr(g, &g->mm.sysmem_flush) >> 8;
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gk20a_writel(g, fb_niso_flush_sysmem_addr_r(), addr);
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}
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void gk20a_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb)
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{
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struct nvgpu_timeout timeout;
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u32 addr_lo;
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u32 data;
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gk20a_dbg_fn("");
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/* pagetables are considered sw states which are preserved after
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prepare_poweroff. When gk20a deinit releases those pagetables,
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common code in vm unmap path calls tlb invalidate that touches
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hw. Use the power_on flag to skip tlb invalidation when gpu
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power is turned off */
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if (!g->power_on)
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return;
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addr_lo = u64_lo32(nvgpu_mem_get_addr(g, pdb) >> 12);
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nvgpu_mutex_acquire(&g->mm.tlb_lock);
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trace_gk20a_mm_tlb_invalidate(g->name);
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nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER);
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do {
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data = gk20a_readl(g, fb_mmu_ctrl_r());
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if (fb_mmu_ctrl_pri_fifo_space_v(data) != 0)
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break;
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nvgpu_udelay(2);
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} while (!nvgpu_timeout_expired_msg(&timeout,
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"wait mmu fifo space"));
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if (nvgpu_timeout_peek_expired(&timeout))
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goto out;
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nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER);
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gk20a_writel(g, fb_mmu_invalidate_pdb_r(),
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fb_mmu_invalidate_pdb_addr_f(addr_lo) |
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nvgpu_aperture_mask(g, pdb,
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fb_mmu_invalidate_pdb_aperture_sys_mem_f(),
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fb_mmu_invalidate_pdb_aperture_vid_mem_f()));
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gk20a_writel(g, fb_mmu_invalidate_r(),
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fb_mmu_invalidate_all_va_true_f() |
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fb_mmu_invalidate_trigger_true_f());
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do {
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data = gk20a_readl(g, fb_mmu_ctrl_r());
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if (fb_mmu_ctrl_pri_fifo_empty_v(data) !=
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fb_mmu_ctrl_pri_fifo_empty_false_f())
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break;
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nvgpu_udelay(2);
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} while (!nvgpu_timeout_expired_msg(&timeout,
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"wait mmu invalidate"));
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trace_gk20a_mm_tlb_invalidate_done(g->name);
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out:
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nvgpu_mutex_release(&g->mm.tlb_lock);
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}
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