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4bb32e33e7
To reduce the duplication of HALs to new chips, this makes pbdma dump_intr_0 as an HAL. JIRA NVGPU-9325 JIRA NVGPU-9064 Change-Id: I737146068cb144165bae8666c04f876aed20a89c Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2847566 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
81 lines
3.1 KiB
C
81 lines
3.1 KiB
C
/*
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* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_PBDMA_GA10B_H
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#define NVGPU_PBDMA_GA10B_H
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#include <nvgpu/types.h>
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#define HW_PBDMA_STRIDE 2048U
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#define HW_PBDMA_BASE 0x040000U
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#define PBDMA_PRI_BASE_INVALID U32_MAX
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#define PBDMA_ID_INVALID U32_MAX
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#define INTR_SIZE 0U
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#define INTR_SET_SIZE 1U
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#define INTR_CLEAR_SIZE 2U
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struct gk20a;
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struct nvgpu_debug_context;
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struct nvgpu_pbdma_status_info;
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struct nvgpu_device;
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void ga10b_pbdma_intr_enable(struct gk20a *g, bool enable);
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int ga10b_pbdma_handle_intr(struct gk20a *g, u32 pbdma_id, bool recover);
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bool ga10b_pbdma_handle_intr_0(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_0,
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u32 *error_notifier);
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bool ga10b_pbdma_handle_intr_1(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_1,
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u32 *error_notifier);
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u32 ga10b_pbdma_read_data(struct gk20a *g, u32 pbdma_id);
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void ga10b_pbdma_reset_header(struct gk20a *g, u32 pbdma_id);
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void ga10b_pbdma_reset_method(struct gk20a *g, u32 pbdma_id,
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u32 pbdma_method_index);
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void ga10b_pbdma_clear_all_intr(struct gk20a *g, u32 pbdma_id);
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void ga10b_pbdma_disable_and_clear_all_intr(struct gk20a *g);
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u32 ga10b_pbdma_channel_fatal_0_intr_descs(void);
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u32 ga10b_pbdma_device_fatal_0_intr_descs(void);
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u32 ga10b_pbdma_set_channel_info_chid(u32 chid);
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u32 ga10b_pbdma_set_intr_notify(u32 eng_intr_vector);
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u32 ga10b_pbdma_set_clear_intr_offsets(struct gk20a *g,
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u32 set_clear_size);
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u32 ga10b_pbdma_get_fc_target(const struct nvgpu_device *dev);
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void ga10b_pbdma_dump_status(struct gk20a *g, struct nvgpu_debug_context *o);
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u32 ga10b_pbdma_get_mmu_fault_id(struct gk20a *g, u32 pbdma_id);
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u32 ga10b_pbdma_get_num_of_pbdmas(void);
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u32 ga10b_pbdma_intr_0_en_set_tree_mask(void);
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u32 ga10b_pbdma_intr_0_en_clear_tree_mask(void);
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u32 ga10b_pbdma_intr_1_en_set_tree_mask(void);
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u32 ga10b_pbdma_intr_1_en_clear_tree_mask(void);
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void ga10b_pbdma_report_error(struct gk20a *g, u32 pbdma_id,
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u32 pbdma_intr_0);
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void ga10b_pbdma_dump_intr_0(struct gk20a *g, u32 pbdma_id,
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u32 pbdma_intr_0);
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#endif /* NVGPU_PBDMA_GA10B_H */
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