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4bb32e33e7
To reduce the duplication of HALs to new chips, this makes pbdma dump_intr_0 as an HAL. JIRA NVGPU-9325 JIRA NVGPU-9064 Change-Id: I737146068cb144165bae8666c04f876aed20a89c Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2847566 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
112 lines
4.0 KiB
C
112 lines
4.0 KiB
C
/*
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* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GOPS_PBDMA_H
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#define NVGPU_GOPS_PBDMA_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_gpfifo_entry;
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struct nvgpu_pbdma_status_info;
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struct nvgpu_device;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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/** NON FUSA */
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struct nvgpu_debug_context;
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struct nvgpu_channel_dump_info;
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struct gops_pbdma_status {
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void (*read_pbdma_status_info)(struct gk20a *g,
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u32 pbdma_id, struct nvgpu_pbdma_status_info *status);
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};
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struct gops_pbdma {
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int (*setup_sw)(struct gk20a *g);
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void (*cleanup_sw)(struct gk20a *g);
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void (*setup_hw)(struct gk20a *g);
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void (*intr_enable)(struct gk20a *g, bool enable);
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u32 (*intr_0_en_set_tree_mask)(void);
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u32 (*intr_0_en_clear_tree_mask)(void);
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u32 (*intr_1_en_set_tree_mask)(void);
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u32 (*intr_1_en_clear_tree_mask)(void);
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bool (*handle_intr_0)(struct gk20a *g,
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u32 pbdma_id, u32 pbdma_intr_0,
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u32 *error_notifier);
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bool (*handle_intr_1)(struct gk20a *g,
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u32 pbdma_id, u32 pbdma_intr_1,
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u32 *error_notifier);
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int (*handle_intr)(struct gk20a *g, u32 pbdma_id, bool recover);
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void (*dump_intr_0)(struct gk20a *g, u32 pbdma_id,
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u32 pbdma_intr_0);
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u32 (*set_clear_intr_offsets) (struct gk20a *g,
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u32 set_clear_size);
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u32 (*get_signature)(struct gk20a *g);
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u32 (*acquire_val)(u64 timeout);
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u32 (*read_data)(struct gk20a *g, u32 pbdma_id);
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void (*reset_header)(struct gk20a *g, u32 pbdma_id);
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u32 (*device_fatal_0_intr_descs)(void);
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u32 (*channel_fatal_0_intr_descs)(void);
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u32 (*restartable_0_intr_descs)(void);
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void (*format_gpfifo_entry)(struct gk20a *g,
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struct nvgpu_gpfifo_entry *gpfifo_entry,
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u64 pb_gpu_va, u32 method_size);
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u32 (*get_gp_base)(u64 gpfifo_base);
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u32 (*get_gp_base_hi)(u64 gpfifo_base, u32 gpfifo_entry);
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u32 (*get_fc_formats)(void);
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u32 (*get_fc_pb_header)(void);
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u32 (*get_fc_subdevice)(void);
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u32 (*get_fc_target)(const struct nvgpu_device *dev);
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u32 (*get_ctrl_hce_priv_mode_yes)(void);
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u32 (*get_userd_aperture_mask)(struct gk20a *g,
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struct nvgpu_mem *mem);
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u32 (*get_userd_addr)(u32 addr_lo);
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u32 (*get_userd_hi_addr)(u32 addr_hi);
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u32 (*get_fc_runlist_timeslice)(void);
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u32 (*get_config_auth_level_privileged)(void);
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u32 (*set_channel_info_veid)(u32 subctx_id);
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u32 (*config_userd_writeback_enable)(u32 v);
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u32 (*allowed_syncpoints_0_index_f)(u32 syncpt);
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u32 (*allowed_syncpoints_0_valid_f)(void);
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u32 (*allowed_syncpoints_0_index_v)(u32 offset);
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u32 (*set_channel_info_chid)(u32 chid);
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u32 (*set_intr_notify)(u32 eng_intr_vector);
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u32 (*get_mmu_fault_id)(struct gk20a *g, u32 pbdma_id);
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u32 (*get_num_of_pbdmas)(void);
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void (*report_error)(struct gk20a *g, u32 pbdma_id,
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u32 pbdma_intr_0);
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/** NON FUSA */
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void (*syncpt_debug_dump)(struct gk20a *g,
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struct nvgpu_debug_context *o,
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struct nvgpu_channel_dump_info *info);
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void (*dump_status)(struct gk20a *g,
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struct nvgpu_debug_context *o);
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#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
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void (*pbdma_force_ce_split)(struct gk20a *g);
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#endif
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};
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/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
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#endif
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