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4c8aadf83c
Remove below variables from struct gr_gk20a u32 bundle_cb_default_size; u32 min_gpm_fifo_depth; u32 bundle_cb_token_limit; u32 attrib_cb_default_size; u32 alpha_cb_default_size; u32 attrib_cb_gfxp_default_size; u32 attrib_cb_gfxp_size; u32 attrib_cb_size; u32 alpha_cb_size; Instead add below hals in hal.gr.init unit to get all of above sizes u32 (*get_bundle_cb_default_size)(struct gk20a *g); u32 (*get_min_gpm_fifo_depth)(struct gk20a *g); u32 (*get_bundle_cb_token_limit)(struct gk20a *g); u32 (*get_attrib_cb_default_size)(struct gk20a *g); u32 (*get_alpha_cb_default_size)(struct gk20a *g); u32 (*get_attrib_cb_gfxp_default_size)(struct gk20a *g); u32 (*get_attrib_cb_gfxp_size)(struct gk20a *g); u32 (*get_attrib_cb_size)(struct gk20a *g, u32 tpc_count); u32 (*get_alpha_cb_size)(struct gk20a *g, u32 tpc_count); u32 (*get_global_attr_cb_size)(struct gk20a *g, u32 max_tpc); Define these hals for all gm20b/gp10b/gv11b/gv100/tu104 chips Also add hal.gr.init support for gv100 chip Remove all accesses to variables from struct gr_gk20a and start using newly defined hals Remove below hals to initialize sizes since they are no more required g->ops.gr.bundle_cb_defaults(g); g->ops.gr.cb_size_default(g); g->ops.gr.calc_global_ctx_buffer_size(g); Also remove definitions of above hals from all the chip files Jira NVGPU-2961 Change-Id: I130b578ababf22328d68fe19df581e46aebeccc9 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2077214 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
46 lines
1.8 KiB
C
46 lines
1.8 KiB
C
/*
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* GP106 GPU GR
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*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_GP106_H
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#define NVGPU_GR_GP106_H
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struct gk20a;
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#define PASCAL_B 0xC197U
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#define PASCAL_COMPUTE_B 0xC1C0U
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bool gr_gp106_is_valid_class(struct gk20a *g, u32 class_num);
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u32 gr_gp106_pagepool_default_size(struct gk20a *g);
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int gr_gp106_handle_sw_method(struct gk20a *g, u32 addr,
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u32 class_num, u32 offset, u32 data);
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int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx,
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struct vm_gk20a *vm, u32 class,
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u32 graphics_preempt_mode,
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u32 compute_preempt_mode);
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u32 gr_gp106_fecs_falcon_base_addr(void);
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u32 gr_gp106_gpccs_falcon_base_addr(void);
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#endif /* NVGPU_GR_GP106_H */
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