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git://nv-tegra.nvidia.com/linux-nvgpu.git
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a9c66768db
Add nvgpu_firmware data structure, and return it instead of Linux struct firmare from nvgpu_request_firmware. Also add abstraction for releasing firmware: nvgpu_release_firmware. JIRA NVGPU-16 Change-Id: I6dae8262957c0d4506f710289e3a43a6c1729fc7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1463538 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
97 lines
2.2 KiB
C
97 lines
2.2 KiB
C
/*
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* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __NVGPU_ACR_H__
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#define __NVGPU_ACR_H__
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#include "gk20a/mm_gk20a.h"
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#include "acr_lsfm.h"
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#include "acr_flcnbl.h"
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#include "acr_objlsfm.h"
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#include "acr_objflcn.h"
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struct nvgpu_firmware;
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#define MAX_SUPPORTED_LSFM 3 /*PMU, FECS, GPCCS*/
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#define ACR_COMPLETION_TIMEOUT_MS 10000 /*in msec */
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#define PMU_SECURE_MODE (0x1)
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#define PMU_LSFM_MANAGED (0x2)
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struct bin_hdr {
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/* 0x10de */
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u32 bin_magic;
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/* versioning of bin format */
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u32 bin_ver;
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/* Entire image size including this header */
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u32 bin_size;
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/*
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* Header offset of executable binary metadata,
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* start @ offset- 0x100 *
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*/
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u32 header_offset;
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/*
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* Start of executable binary data, start @
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* offset- 0x200
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*/
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u32 data_offset;
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/* Size of executable binary */
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u32 data_size;
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};
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struct acr_fw_header {
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u32 sig_dbg_offset;
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u32 sig_dbg_size;
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u32 sig_prod_offset;
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u32 sig_prod_size;
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u32 patch_loc;
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u32 patch_sig;
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u32 hdr_offset; /* This header points to acr_ucode_header_t210_load */
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u32 hdr_size; /* Size of above header */
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};
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struct wpr_carveout_info {
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u64 wpr_base;
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u64 nonwpr_base;
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u64 size;
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};
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struct acr_desc {
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struct nvgpu_mem ucode_blob;
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struct nvgpu_mem wpr_dummy;
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struct bin_hdr *bl_bin_hdr;
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struct hsflcn_bl_desc *pmu_hsbl_desc;
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struct bin_hdr *hsbin_hdr;
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struct acr_fw_header *fw_hdr;
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u32 pmu_args;
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struct nvgpu_firmware *acr_fw;
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union{
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struct flcn_acr_desc *acr_dmem_desc;
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struct flcn_acr_desc_v1 *acr_dmem_desc_v1;
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};
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struct nvgpu_mem acr_ucode;
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struct nvgpu_firmware *hsbl_fw;
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struct nvgpu_mem hsbl_ucode;
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union {
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struct flcn_bl_dmem_desc bl_dmem_desc;
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struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1;
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};
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struct nvgpu_firmware *pmu_fw;
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struct nvgpu_firmware *pmu_desc;
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u32 capabilities;
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};
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#endif /*__NVGPU_ACR_H__*/
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