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d2de17bfb0
GPC2CLK has been replaced with GPCCLK on user API. Remove related definition from kernel API. GPCLCK and MCLK are currently assigned EQU values in kernel API. We want to move to a simple enumeration as used in nvrm_gpu. During the transition, an alias value will be defined for each clock, and kernel will accept both. Jira DNVGPU-210 Jira DNVGPU-211 Change-Id: I944fe78be9f810279f7a69964be7cda9b9c8d40d Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1292593 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
74 lines
2.3 KiB
C
74 lines
2.3 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include "gk20a/gk20a.h"
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#ifndef _CLK_ARB_H_
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#define _CLK_ARB_H_
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struct nvgpu_clk_arb;
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struct nvgpu_clk_session;
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int nvgpu_clk_arb_init_arbiter(struct gk20a *g);
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int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
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u16 *min_mhz, u16 *max_mhz);
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int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g,
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u32 api_domain, u16 *actual_mhz);
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int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g,
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u32 api_domain, u16 *effective_mhz);
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int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g,
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u32 api_domain, u32 *max_points, u16 *fpoints);
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u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g);
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bool nvgpu_clk_arb_is_valid_domain(struct gk20a *g, u32 api_domain);
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void nvgpu_clk_arb_cleanup_arbiter(struct gk20a *g);
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int nvgpu_clk_arb_install_session_fd(struct gk20a *g,
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struct nvgpu_clk_session *session);
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int nvgpu_clk_arb_init_session(struct gk20a *g,
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struct nvgpu_clk_session **_session);
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void nvgpu_clk_arb_release_session(struct gk20a *g,
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struct nvgpu_clk_session *session);
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int nvgpu_clk_arb_commit_request_fd(struct gk20a *g,
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struct nvgpu_clk_session *session, int request_fd);
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int nvgpu_clk_arb_set_session_target_mhz(struct nvgpu_clk_session *session,
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int fd, u32 api_domain, u16 target_mhz);
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int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session,
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u32 api_domain, u16 *target_mhz);
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int nvgpu_clk_arb_install_event_fd(struct gk20a *g,
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struct nvgpu_clk_session *session, int *event_fd, u32 alarm_mask);
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int nvgpu_clk_arb_install_request_fd(struct gk20a *g,
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struct nvgpu_clk_session *session, int *event_fd);
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void nvgpu_clk_arb_schedule_vf_table_update(struct gk20a *g);
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int nvgpu_clk_arb_get_current_pstate(struct gk20a *g);
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void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock);
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void nvgpu_clk_arb_schedule_alarm(struct gk20a *g, u32 alarm);
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#endif /* _CLK_ARB_H_ */
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