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b17d9708c9
JIRA DNVGPU-45 Change-Id: I237ce81e31b036c05c82d46eea8694ffe1c2e3df Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Signed-off-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1205849 (cherry picked from commit 9a4006f76b75a8ad525e7aa5ad1f609aaae49126) Reviewed-on: http://git-master/r/1227256 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
154 lines
4.9 KiB
C
154 lines
4.9 KiB
C
/*
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* general p state infrastructure
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*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ctrlclk_h_
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#define _ctrlclk_h_
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#include "ctrlboardobj.h"
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#include "ctrlclkavfs.h"
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#include "ctrlvolt.h"
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#define CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS 4
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/* valid clock domain values */
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#define CTRL_CLK_DOMAIN_MCLK (0x00000010)
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#define CTRL_CLK_DOMAIN_DISPCLK (0x00000040)
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#define CTRL_CLK_DOMAIN_GPC2CLK (0x00010000)
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#define CTRL_CLK_DOMAIN_XBAR2CLK (0x00040000)
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#define CTRL_CLK_DOMAIN_SYS2CLK (0x00080000)
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#define CTRL_CLK_DOMAIN_HUB2CLK (0x00100000)
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#define CTRL_CLK_DOMAIN_PWRCLK (0x00800000)
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#define CTRL_CLK_DOMAIN_NVDCLK (0x01000000)
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#define CTRL_CLK_DOMAIN_PCIEGENCLK (0x02000000)
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#define CTRL_CLK_DOMAIN_GPCCLK (0x10000000)
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#define CTRL_CLK_DOMAIN_XBARCLK (0x20000000)
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#define CTRL_CLK_DOMAIN_SYSCLK (0x40000000)
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#define CTRL_CLK_DOMAIN_HUBCLK (0x80000000)
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#define CTRL_CLK_CLK_DOMAIN_TYPE_3X 0x01
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#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED 0x02
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#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG 0x03
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#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER 0x04
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#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE 0x05
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#define CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID 0xFF
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#define CTRL_CLK_CLK_DOMAIN_INDEX_INVALID 0xFF
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#define CTRL_CLK_CLK_PROG_TYPE_1X 0x00
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#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER 0x01
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#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_RATIO 0x02
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#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE 0x03
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#define CTRL_CLK_CLK_PROG_TYPE_UNKNOWN 255
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/*!
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* Enumeration of CLK_PROG source types.
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*/
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#define CTRL_CLK_PROG_1X_SOURCE_PLL 0x00
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#define CTRL_CLK_PROG_1X_SOURCE_ONE_SOURCE 0x01
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#define CTRL_CLK_PROG_1X_SOURCE_FLL 0x02
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#define CTRL_CLK_PROG_1X_SOURCE_INVALID 255
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#define CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES 4
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#define CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES 6
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#define CTRL_CLK_CLK_VF_POINT_IDX_INVALID 255
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#define CTRL_CLK_CLK_VF_POINT_TYPE_FREQ 0x00
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#define CTRL_CLK_CLK_VF_POINT_TYPE_VOLT 0x01
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#define CTRL_CLK_CLK_VF_POINT_TYPE_UNKNOWN 255
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struct ctrl_clk_clk_prog_1x_master_source_fll {
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u32 base_vfsmooth_volt_uv;
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u32 max_vf_ramprate;
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u32 max_freq_stepsize_mhz;
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};
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union ctrl_clk_clk_prog_1x_master_source_data {
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struct ctrl_clk_clk_prog_1x_master_source_fll fll;
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};
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struct ctrl_clk_clk_vf_point_info_freq {
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u16 freq_mhz;
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};
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struct ctrl_clk_clk_vf_point_info_volt {
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u32 sourceVoltageuV;
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u8 vfGainVfeEquIdx;
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u8 clkDomainIdx;
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};
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struct ctrl_clk_clk_prog_1x_master_vf_entry {
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u8 vfe_idx;
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u8 gain_vfe_idx;
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u8 vf_point_idx_first;
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u8 vf_point_idx_last;
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};
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struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry {
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u8 clk_dom_idx;
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u8 ratio;
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};
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struct ctrl_clk_clk_prog_1x_master_table_slave_entry {
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u8 clk_dom_idx;
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u16 freq_mhz;
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};
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struct ctrl_clk_clk_prog_1x_source_pll {
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u8 pll_idx;
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u8 freq_step_size_mhz;
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};
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struct ctrl_clk_clk_delta {
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int freq_delta_khz;
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int volt_deltauv[CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS];
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};
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union ctrl_clk_clk_prog_1x_source_data {
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struct ctrl_clk_clk_prog_1x_source_pll pll;
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};
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struct ctrl_clk_vf_pair {
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u16 freq_mhz;
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u32 voltage_uv;
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};
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struct ctrl_clk_clk_domain_list_item {
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u32 clk_domain;
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u32 clk_freq_khz;
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u32 clk_flags;
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u8 current_regime_id;
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u8 target_regime_id;
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};
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#define CTRL_CLK_VF_PAIR_FREQ_MHZ_GET(pvfpair) \
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((pvfpair)->freq_mhz)
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#define CTRL_CLK_VF_PAIR_VOLTAGE_UV_GET(pvfpair) \
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((pvfpair)->voltage_uv)
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#define CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(pvfpair, _freqmhz) \
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(((pvfpair)->freq_mhz) = (_freqmhz))
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#define CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(pvfpair, _freqmhz) \
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(((pvfpair)->freq_mhz) = (_freqmhz))
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#define CTRL_CLK_VF_PAIR_VOLTAGE_UV_SET(pvfpair, _voltageuv) \
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(((pvfpair)->voltage_uv) = (_voltageuv))
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#endif
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