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865514be2d
Move the gp10b HW headers to a new directory specially for them: include/nvgpu/hw/gp10b And change the code to include like so: #include <nvgpu/hw/gp10b/hw_fb_gp10b.h> This is part of the process to restructure the nvgpu driver. Bug 1799159 Change-Id: Ic80ea5b7f5c280839e502e2178a345181f7a7ef9 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1280326 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
132 lines
4.5 KiB
C
132 lines
4.5 KiB
C
/*
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* drivers/gpu/nvgpu/gm20b/therm_gk20a.c
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*
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* GP10B Therm
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*
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* Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include "gk20a/gk20a.h"
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#include <nvgpu/hw/gp10b/hw_therm_gp10b.h>
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static int gp10b_init_therm_setup_hw(struct gk20a *g)
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{
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u32 v;
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gk20a_dbg_fn("");
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/* program NV_THERM registers */
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gk20a_writel(g, therm_use_a_r(), therm_use_a_ext_therm_0_enable_f() |
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therm_use_a_ext_therm_1_enable_f() |
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therm_use_a_ext_therm_2_enable_f());
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gk20a_writel(g, therm_evt_ext_therm_0_r(),
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therm_evt_ext_therm_0_slow_factor_f(0x2));
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gk20a_writel(g, therm_evt_ext_therm_1_r(),
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therm_evt_ext_therm_1_slow_factor_f(0x6));
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gk20a_writel(g, therm_evt_ext_therm_2_r(),
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therm_evt_ext_therm_2_slow_factor_f(0xe));
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gk20a_writel(g, therm_grad_stepping_table_r(0),
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therm_grad_stepping_table_slowdown_factor0_f(
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therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f()) |
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therm_grad_stepping_table_slowdown_factor1_f(
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therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f()) |
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therm_grad_stepping_table_slowdown_factor2_f(
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therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f()) |
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therm_grad_stepping_table_slowdown_factor3_f(
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therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
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therm_grad_stepping_table_slowdown_factor4_f(
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therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
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gk20a_writel(g, therm_grad_stepping_table_r(1),
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therm_grad_stepping_table_slowdown_factor0_f(
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therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
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therm_grad_stepping_table_slowdown_factor1_f(
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therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
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therm_grad_stepping_table_slowdown_factor2_f(
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therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
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therm_grad_stepping_table_slowdown_factor3_f(
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therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
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therm_grad_stepping_table_slowdown_factor4_f(
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therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
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v = gk20a_readl(g, therm_clk_timing_r(0));
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v |= therm_clk_timing_grad_slowdown_enabled_f();
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gk20a_writel(g, therm_clk_timing_r(0), v);
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v = gk20a_readl(g, therm_config2_r());
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v |= therm_config2_grad_enable_f(1);
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v |= therm_config2_slowdown_factor_extended_f(1);
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gk20a_writel(g, therm_config2_r(), v);
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gk20a_writel(g, therm_grad_stepping1_r(),
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therm_grad_stepping1_pdiv_duration_f(32));
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v = gk20a_readl(g, therm_grad_stepping0_r());
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v |= therm_grad_stepping0_feature_enable_f();
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gk20a_writel(g, therm_grad_stepping0_r(), v);
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return 0;
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}
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static int gp10b_elcg_init_idle_filters(struct gk20a *g)
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{
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u32 gate_ctrl, idle_filter;
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u32 engine_id;
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u32 active_engine_id = 0;
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struct fifo_gk20a *f = &g->fifo;
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gk20a_dbg_fn("");
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for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
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active_engine_id = f->active_engines_list[engine_id];
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gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
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if (tegra_platform_is_linsim()) {
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gate_ctrl = set_field(gate_ctrl,
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therm_gate_ctrl_eng_delay_after_m(),
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therm_gate_ctrl_eng_delay_after_f(4));
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}
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/* 2 * (1 << 9) = 1024 clks */
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gate_ctrl = set_field(gate_ctrl,
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therm_gate_ctrl_eng_idle_filt_exp_m(),
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therm_gate_ctrl_eng_idle_filt_exp_f(9));
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gate_ctrl = set_field(gate_ctrl,
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therm_gate_ctrl_eng_idle_filt_mant_m(),
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therm_gate_ctrl_eng_idle_filt_mant_f(2));
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gate_ctrl = set_field(gate_ctrl,
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therm_gate_ctrl_eng_delay_before_m(),
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therm_gate_ctrl_eng_delay_before_f(4));
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gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
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}
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/* default fecs_idle_filter to 0 */
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idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
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idle_filter &= ~therm_fecs_idle_filter_value_m();
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gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
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/* default hubmmu_idle_filter to 0 */
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idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
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idle_filter &= ~therm_hubmmu_idle_filter_value_m();
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gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
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gk20a_dbg_fn("done");
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return 0;
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}
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void gp10b_init_therm_ops(struct gpu_ops *gops)
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{
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gops->therm.init_therm_setup_hw = gp10b_init_therm_setup_hw;
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gops->therm.elcg_init_idle_filters = gp10b_elcg_init_idle_filters;
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}
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