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4df6cd4a34
Generate a ctxsw channel reset when engine needs to be reset. This event is generated by the driver, while other events are generated by FECS. JIRA ELVR-314 Change-Id: I7791cf3e538782464c37c442c871acb177484566 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1129029 (cherry picked from commit 114038a1a5d9e8941bc53f3e95115b01dd1f8c6e) Reviewed-on: http://git-master/r/1134379 (cherry picked from commit 15fa2a7b48a0937dfd449ca0c4ed5ad3a863d6bf) Reviewed-on: http://git-master/r/1123916 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
49 lines
1.7 KiB
C
49 lines
1.7 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __CTXSW_TRACE_GK20A_H
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#define __CTXSW_TRACE_GK20A_H
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#define GK20A_CTXSW_TRACE_NUM_DEVS 1
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struct gk20a;
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struct gpu_ops;
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struct nvgpu_ctxsw_trace_entry;
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struct channel_gk20a;
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struct channel_ctx_gk20a;
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struct gk20a_ctxsw_dev;
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struct gk20a_fecs_trace;
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struct tsg_gk20a;
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int gk20a_ctxsw_dev_release(struct inode *inode, struct file *filp);
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int gk20a_ctxsw_dev_open(struct inode *inode, struct file *filp);
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long gk20a_ctxsw_dev_ioctl(struct file *filp,
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unsigned int cmd, unsigned long arg);
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ssize_t gk20a_ctxsw_dev_read(struct file *, char __user *, size_t, loff_t *);
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unsigned int gk20a_ctxsw_dev_poll(struct file *, struct poll_table_struct *);
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int gk20a_ctxsw_dev_mmap(struct file *, struct vm_area_struct *);
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int gk20a_ctxsw_trace_init(struct gk20a *);
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int gk20a_ctxsw_trace_setup(struct gk20a *, void *ctx_ptr);
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void gk20a_ctxsw_trace_cleanup(struct gk20a *);
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int gk20a_ctxsw_trace_write(struct gk20a *, struct nvgpu_ctxsw_trace_entry *);
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void gk20a_ctxsw_trace_wake_up(struct gk20a *g, int vmid);
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void gk20a_ctxsw_trace_init_ops(struct gpu_ops *ops);
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void gk20a_ctxsw_trace_channel_reset(struct gk20a *g, struct channel_gk20a *ch);
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void gk20a_ctxsw_trace_tsg_reset(struct gk20a *g, struct tsg_gk20a *tsg);
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#endif /* __CTXSW_TRACE_GK20A_H */
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