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999eabbcd7
MISRA rule 10.1 doesn't allow the usage of non-boolean variables as booleans. Fix violations where a variable of type non-boolean is used as a boolean and changed few instances of BIT() to BIT32() or BIT64(). JIRA NVGPU-646 Change-Id: I100606a69717c12839aa9c35e7bf6c18749db56e Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809836 GVS: Gerrit_Virtual_Submit Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
76 lines
2.5 KiB
C
76 lines
2.5 KiB
C
/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/timers.h>
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#include <nvgpu/mm.h>
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#include <nvgpu/gk20a.h>
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#include "bus_tu104.h"
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#include "tu104/func_tu104.h"
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#include <nvgpu/hw/tu104/hw_bus_tu104.h>
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#include <nvgpu/hw/tu104/hw_func_tu104.h>
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int bus_tu104_bar2_bind(struct gk20a *g, struct nvgpu_mem *bar2_inst)
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{
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struct nvgpu_timeout timeout;
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int err = 0;
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u64 iova = nvgpu_inst_block_addr(g, bar2_inst);
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u32 ptr_v = (u32)(iova >> bus_bar2_block_ptr_shift_v());
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nvgpu_log_info(g, "bar2 inst block ptr: 0x%08x", ptr_v);
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err = nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER);
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if (err != 0) {
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return err;
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}
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nvgpu_func_writel(g, func_priv_bar2_block_r(),
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nvgpu_aperture_mask(g, bar2_inst,
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bus_bar2_block_target_sys_mem_ncoh_f(),
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bus_bar2_block_target_sys_mem_coh_f(),
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bus_bar2_block_target_vid_mem_f()) |
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bus_bar2_block_mode_virtual_f() |
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bus_bar2_block_ptr_f(ptr_v));
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do {
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u32 val = nvgpu_func_readl(g,
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func_priv_bind_status_r());
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bool pending = (bus_bind_status_bar2_pending_v(val) ==
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bus_bind_status_bar2_pending_busy_v());
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bool outstanding = (bus_bind_status_bar2_outstanding_v(val) ==
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bus_bind_status_bar2_outstanding_true_v());
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if (!pending && !outstanding) {
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break;
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}
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nvgpu_udelay(5);
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} while (nvgpu_timeout_expired(&timeout) == 0);
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if (nvgpu_timeout_peek_expired(&timeout) != 0) {
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err = -EINVAL;
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}
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return err;
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}
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