Konsta Holtta 4e6d9afab8 gpu: nvgpu: store ch ptr in gr isr data ...

Store a channel pointer that is either NULL or a referenced channel to
avoid confusion about channel ownership. A pure channel ID is dangerous.

Jira NVGPU-1460

Change-Id: I6f7b4f80cf39abc290ce9153ec6bf5b62918da97
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1955401
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2018-11-27 12:24:47 -08:00

..

ce2_gk20a.c

gpu: nvgpu: MISRA 14.4 bitwise operation as boolean

2018-11-27 11:14:12 -08:00

ce2_gk20a.h

gpu: nvgpu: MISRA 14.4 bitwise operation as boolean

2018-11-27 11:14:12 -08:00

clk_gk20a.h

gpu: nvgpu: gk20a: fix MISRA 10.4 Violations [2/2]

2018-11-09 13:27:12 -08:00

fecs_trace_gk20a.c

gpu: nvgpu: pass gr ctx to fecs_trace_bind_channel

2018-11-23 04:30:28 -08:00

fecs_trace_gk20a.h

gpu: nvgpu: pass gr ctx to fecs_trace_bind_channel

2018-11-23 04:30:28 -08:00

fence_gk20a.c

gpu: nvgpu: Fix MISRA rule 8.8 and 8.10

2018-11-09 13:27:39 -08:00

fence_gk20a.h

gpu: nvgpu: Fix MISRA rule 8.8 and 8.10

2018-11-09 13:27:39 -08:00

fifo_gk20a.c

gpu: nvgpu: add safe channel id lookup

2018-11-27 12:24:38 -08:00

fifo_gk20a.h

gpu: nvgpu: Fix MISRA rule 8.3 violations

2018-11-12 22:33:18 -08:00

gr_gk20a.c

gpu: nvgpu: store ch ptr in gr isr data

2018-11-27 12:24:47 -08:00

gr_gk20a.h

gpu: nvgpu: store ch ptr in gr isr data

2018-11-27 12:24:47 -08:00

gr_pri_gk20a.h

gpu: nvgpu: gk20a: fix MISRA 10.4 Violations [1/2]

2018-11-09 13:27:08 -08:00

mm_gk20a.c

gpu: nvgpu: Fix MISRA 12.2 misc bit shift errors

2018-11-14 09:14:37 -08:00

mm_gk20a.h

gpu: nvgpu: Fix MISRA rule 8.3 violations

2018-11-15 15:35:47 -08:00

regops_gk20a.c

gpu: nvgpu: MISRA 11.8 const usage fixes

2018-11-15 09:34:36 -08:00

regops_gk20a.h

gpu: nvgpu: gk20a: fix MISRA 10.4 Violations [2/2]

2018-11-09 13:27:12 -08:00