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63d1b7113a
MISRA rule 12.2 states that the right hand operand of a shift operator shall lie in the range zero to one less than the width in bits of the essential type of the left hand operand. This patch will fix these violations by casting them to an appropriate type or using the relevant BITxx() macros. JIRA NVGPU-666 Change-Id: I57b6081e9bd98c45ca9f7aa5f35e1d2d66ed0134 Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1945655 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
51 lines
2.3 KiB
C
51 lines
2.3 KiB
C
/*
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* GV11B/GV100 Graphics Context Pri Register Addressing
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*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef GR_PRI_GV11B_H
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#define GR_PRI_GV11B_H
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/*
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* These convenience macros are generally for use in the management/modificaiton
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* of the context state store for gr/compute contexts.
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*/
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/* Broadcast PMM defines */
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#define NV_PERF_PMMFBP_FBPGS_LTC 0x00250800U
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#define NV_PERF_PMMFBP_FBPGS_ROP 0x00250A00U
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#define NV_PERF_PMMGPC_GPCGS_GPCTPCA 0x00250000U
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#define NV_PERF_PMMGPC_GPCGS_GPCTPCB 0x00250200U
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#define NV_PERF_PMMGPC_GPCS 0x00278000U
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#define NV_PERF_PMMFBP_FBPS 0x0027C000U
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#define PRI_PMMGS_ADDR_WIDTH 9
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#define PRI_PMMS_ADDR_WIDTH 14
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/* Get the offset to be added to the chiplet base addr to get the unicast address */
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#define PRI_PMMGS_OFFSET_MASK(addr) ((addr) & (BIT32(PRI_PMMGS_ADDR_WIDTH) - 1U))
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#define PRI_PMMGS_BASE_ADDR_MASK(addr) ((addr) & (~(BIT32(PRI_PMMGS_ADDR_WIDTH) - 1U)))
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#define PRI_PMMS_ADDR_MASK(addr) ((addr) & (BIT32(PRI_PMMS_ADDR_WIDTH) - 1U))
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#define PRI_PMMS_BASE_ADDR_MASK(addr) ((addr) & (~(BIT32(PRI_PMMS_ADDR_WIDTH) - 1U)))
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#endif /* GR_PRI_GV11B_H */
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