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1023c6af14
MISRA rule 14.4 doesn't allow the usage of non-boolean variable as boolean in the controlling expression of an if statement or an iteration statement. Fix violations where a non-boolean variable is used as a boolean in the controlling expression of if and loop statements. JIRA NVGPU-1022 Change-Id: I61a2d24830428ffc2655bd9c45bb5403c7f22c09 Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1943058 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
102 lines
3.2 KiB
C
102 lines
3.2 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_LPWR_H
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#define NVGPU_LPWR_H
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#define MAX_SWASR_MCLK_FREQ_WITHOUT_WR_TRAINING_MAXWELL_MHZ 540
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#define NV_PMU_PG_PARAM_MCLK_CHANGE_MS_SWASR_ENABLED BIT(0x1)
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#define NV_PMU_PG_PARAM_MCLK_CHANGE_GDDR5_WR_TRAINING_ENABLED BIT(0x3)
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#define LPWR_ENTRY_COUNT_MAX 0x06
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#define LPWR_VBIOS_IDX_ENTRY_COUNT_MAX (LPWR_ENTRY_COUNT_MAX)
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#define LPWR_VBIOS_IDX_ENTRY_RSVD \
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(LPWR_VBIOS_IDX_ENTRY_COUNT_MAX - 1)
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#define LPWR_VBIOS_BASE_SAMPLING_PERIOD_DEFAULT (500)
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struct nvgpu_lpwr_bios_idx_entry {
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u8 pcie_idx;
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u8 gr_idx;
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u8 ms_idx;
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u8 di_idx;
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u8 gc6_idx;
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};
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struct nvgpu_lpwr_bios_idx_data {
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u16 base_sampling_period;
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struct nvgpu_lpwr_bios_idx_entry entry[LPWR_VBIOS_IDX_ENTRY_COUNT_MAX];
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};
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#define LPWR_VBIOS_MS_ENTRY_COUNT_MAX (LPWR_ENTRY_COUNT_MAX)
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struct nvgpu_lpwr_bios_ms_entry {
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bool ms_enabled;
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u32 feature_mask;
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u32 asr_efficiency_thresholdl;
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u16 dynamic_current_logic;
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u16 dynamic_current_sram;
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};
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struct nvgpu_lpwr_bios_ms_data {
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u8 default_entry_idx;
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u32 idle_threshold_us;
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struct nvgpu_lpwr_bios_ms_entry entry[LPWR_VBIOS_MS_ENTRY_COUNT_MAX];
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};
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#define LPWR_VBIOS_GR_ENTRY_COUNT_MAX (LPWR_ENTRY_COUNT_MAX)
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struct nvgpu_lpwr_bios_gr_entry {
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bool gr_enabled;
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u32 feature_mask;
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};
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struct nvgpu_lpwr_bios_gr_data {
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u8 default_entry_idx;
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u32 idle_threshold_us;
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u8 adaptive_gr_multiplier;
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struct nvgpu_lpwr_bios_gr_entry entry[LPWR_VBIOS_GR_ENTRY_COUNT_MAX];
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};
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struct nvgpu_lpwr_bios_data {
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struct nvgpu_lpwr_bios_idx_data idx;
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struct nvgpu_lpwr_bios_ms_data ms;
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struct nvgpu_lpwr_bios_gr_data gr;
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};
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struct obj_lwpr {
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struct nvgpu_lpwr_bios_data lwpr_bios_data;
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u32 mclk_change_cache;
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};
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int nvgpu_lpwr_pg_setup(struct gk20a *g);
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int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate);
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int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock);
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int nvgpu_lpwr_disable_pg(struct gk20a *g, bool pstate_lock);
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bool nvgpu_lpwr_is_mscg_supported(struct gk20a *g, u32 pstate_num);
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bool nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num);
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u32 nvgpu_lpwr_post_init(struct gk20a *g);
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#endif /* NVGPU_LPWR_H */
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