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GPCCS ucode is expecting the SM ID programmed in GPM and CWD registers to be in sync. So create a hal called gr.init.load_sm_id_config() for the sm_id programming for the CWD registers and invoke them before the ucode load. Initialize this hal only for the required GPUs. JIRA NVGPU-9757 Change-Id: Ib0984fd6326c37e0c2a06123041032575a23ec04 Signed-off-by: Ramalingam C <ramalingamc@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2864999 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>