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b4ec1c5dff
Renamed and moved from fifo to channel gk20a_debug_dump_all_channel_status_ramfc -> nvgpu_channel_debug_dump_all gk20a_dump_channel_status_ramfc -> gk20a_channel_debug_dump gv11b_dump_channel_status_ramfc -> gv11b_channel_debug_dump Moved nvgpu_channel_dump_info struct to channel.h Moved nvgpu_channel_hw_state struct to channel.h Moved dump_channel_status_ramfc fifo ops to channel ops as debug_dump JIRA NVGPU-2978 Change-Id: I696e5029d9e6ca4dc3516651b4d4f5230fe8b0b0 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2092709 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
64 lines
2.5 KiB
C
64 lines
2.5 KiB
C
/*
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* GV11B Fifo
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*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef FIFO_GV11B_H
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#define FIFO_GV11B_H
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#define PBDMA_SUBDEVICE_ID 1U
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#define FIFO_INVAL_PBDMA_ID (~U32(0U))
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#define FIFO_INVAL_VEID (~U32(0U))
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#define CHANNEL_INFO_VEID0 0U
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#define MAX_PRE_SI_RETRIES 200000U /* 1G/500KHz * 100 */
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struct gpu_ops;
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void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g,
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struct tsg_gk20a *tsg,
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u32 faulted_pbdma, u32 faulted_engine);
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void gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(struct gk20a *g,
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u32 mmu_fault_id, u32 *active_engine_id, u32 *veid, u32 *pbdma_id);
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int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id,
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unsigned int id_type);
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int gv11b_fifo_preempt_channel(struct gk20a *g, struct channel_gk20a *ch);
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int gv11b_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg);
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void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask,
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u32 id, unsigned int id_type, unsigned int rc_type,
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struct mmu_fault_info *mmfault);
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void gv11b_fifo_teardown_mask_intr(struct gk20a *g);
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void gv11b_fifo_teardown_unmask_intr(struct gk20a *g);
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void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f);
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int gv11b_init_fifo_reset_enable_hw(struct gk20a *g);
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int gv11b_init_fifo_setup_hw(struct gk20a *g);
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u32 gv11b_fifo_get_preempt_timeout(struct gk20a *g);
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void gv11b_ring_channel_doorbell(struct channel_gk20a *c);
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u64 gv11b_fifo_usermode_base(struct gk20a *g);
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u32 gv11b_fifo_doorbell_token(struct channel_gk20a *c);
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#endif
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