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66cb9495a5
Moved -mmu_fault_pending mm ops to is_mmu_fault_pending mc ops -mmu_fault_pending fb ops to is_mmu_fault_pending fb.intr ops. This is needed to check if mmu fault intr is pending for volta onwards. Added is_mmu_fault_pending fifo ops. This is needed to check if mmu fault interrupt is pending for chips prior to volta JIRA NVGPU-1313 Change-Id: Ie8e778387cd486cb19b18c4aee734c581dcd9229 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2094895 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
43 lines
1.7 KiB
C
43 lines
1.7 KiB
C
/*
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* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_FIFO_INTR_GK20A_H
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#define NVGPU_FIFO_INTR_GK20A_H
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#include <nvgpu/types.h>
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struct gk20a;
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void gk20a_fifo_intr_0_enable(struct gk20a *g, bool enable);
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void gk20a_fifo_intr_1_enable(struct gk20a *g, bool enable);
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void gk20a_fifo_intr_0_isr(struct gk20a *g);
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u32 gk20a_fifo_intr_1_isr(struct gk20a *g);
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void gk20a_fifo_intr_handle_chsw_error(struct gk20a *g);
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void gk20a_fifo_intr_handle_runlist_event(struct gk20a *g);
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u32 gk20a_fifo_pbdma_isr(struct gk20a *g);
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bool gk20a_fifo_handle_sched_error(struct gk20a *g);
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bool gk20a_fifo_is_mmu_fault_pending(struct gk20a *g);
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#endif /* NVGPU_FIFO_INTR_GK20A_H */
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