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eaab8ad1f2
a) free_channel_ctx_header is used to free the channel's underlying subctx and belongs to the hal.channel unit instead of fifo. Moved the same and renamed the HAL ops to free_ctx_header. The function gv11b_free_subctx_header is moved to channel_gv11b.* files and also renamed to gv11b_channel_free_subctx_header. b) ch_abort_clean_up is moved to hal.channel unit c) channel_resume and channel_suspend are used to resume and suspend all the serviceable channels. This belongs to hal.channel unit and are moved from the hal.fifo unit. The HAL ops channel_resume and channel_suspend are renamed to resume_all_serviceable_ch and suspend_all_serviceable_ch respectively. gk20a_channel_resume and gk20a_channel_suspend are also renamed to nvgpu_channel_resume_all_serviceable_ch and nvgpu_channel_suspend_all_serviceable_ch respectively. d) set_error_notifier HAL ops belongs to hal.channel and is moved accordingly. Jira NVGPU-2978 Change-Id: Icb52245cacba3004e2fd32519029a1acff60c23c Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2083593 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
65 lines
2.2 KiB
C
65 lines
2.2 KiB
C
/*
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* GV11B USERD
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*
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* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/io.h>
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
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#include "userd_gv11b.h"
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u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *ch)
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{
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struct nvgpu_mem *mem = ch->userd_mem;
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u32 offset = ch->userd_offset / U32(sizeof(u32));
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return nvgpu_mem_rd32(g, mem, offset + ram_userd_gp_get_w());
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}
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u64 gv11b_userd_pb_get(struct gk20a *g, struct channel_gk20a *ch)
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{
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struct nvgpu_mem *mem = ch->userd_mem;
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u32 offset = ch->userd_offset / U32(sizeof(u32));
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u32 lo, hi;
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lo = nvgpu_mem_rd32(g, mem, offset + ram_userd_get_w());
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hi = nvgpu_mem_rd32(g, mem, offset + ram_userd_get_hi_w());
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return ((u64)hi << 32) | lo;
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}
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void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *ch)
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{
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struct nvgpu_mem *mem = ch->userd_mem;
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u32 offset = ch->userd_offset / U32(sizeof(u32));
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nvgpu_mem_wr32(g, mem, offset + ram_userd_gp_put_w(), ch->gpfifo.put);
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/* Commit everything to GPU. */
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nvgpu_mb();
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g->ops.fifo.ring_channel_doorbell(ch);
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}
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