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89aecd1202
Added interface to allow kernel to create privileged CE channels for page migration and clearing support between sysmem and videmem. JIRA DNVGPU-53 Change-Id: I3e18d18403809c9e64fa45d40b6c4e3844992506 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1173085 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
156 lines
4.5 KiB
C
156 lines
4.5 KiB
C
/*
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* drivers/video/tegra/host/gk20a/fifo_gk20a.h
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*
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* GK20A graphics copy engine (gr host)
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*
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* Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef __CE2_GK20A_H__
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#define __CE2_GK20A_H__
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#include "channel_gk20a.h"
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#include "tsg_gk20a.h"
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void gk20a_init_ce2(struct gpu_ops *gops);
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void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
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void gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
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/* CE command utility macros */
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#define NVGPU_CE_LOWER_ADDRESS_OFFSET_MASK 0xffffffff
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#define NVGPU_CE_UPPER_ADDRESS_OFFSET_MASK 0xff
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#define NVGPU_CE_COMMAND_BUF_SIZE 4096
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#define NVGPU_CE_MAX_COMMAND_BUFF_SIZE_PER_KICKOFF 128
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#define NVGPU_CE_MAX_COMMAND_BUFF_SIZE_FOR_TRACING 8
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typedef void (*ce_event_callback)(u32 ce_ctx_id, u32 ce_event_flag);
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/* dma launch_flags */
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enum {
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/* location */
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NVGPU_CE_SRC_LOCATION_COHERENT_SYSMEM = (1 << 0),
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NVGPU_CE_SRC_LOCATION_NONCOHERENT_SYSMEM = (1 << 1),
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NVGPU_CE_SRC_LOCATION_LOCAL_FB = (1 << 2),
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NVGPU_CE_DST_LOCATION_COHERENT_SYSMEM = (1 << 3),
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NVGPU_CE_DST_LOCATION_NONCOHERENT_SYSMEM = (1 << 4),
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NVGPU_CE_DST_LOCATION_LOCAL_FB = (1 << 5),
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/* memory layout */
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NVGPU_CE_SRC_MEMORY_LAYOUT_PITCH = (1 << 6),
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NVGPU_CE_SRC_MEMORY_LAYOUT_BLOCKLINEAR = (1 << 7),
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NVGPU_CE_DST_MEMORY_LAYOUT_PITCH = (1 << 8),
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NVGPU_CE_DST_MEMORY_LAYOUT_BLOCKLINEAR = (1 << 9),
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/* transfer type */
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NVGPU_CE_DATA_TRANSFER_TYPE_PIPELINED = (1 << 10),
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NVGPU_CE_DATA_TRANSFER_TYPE_NON_PIPELINED = (1 << 11),
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};
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/* CE operation mode */
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enum {
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NVGPU_CE_PHYS_MODE_TRANSFER = (1 << 0),
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NVGPU_CE_MEMSET = (1 << 1),
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};
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/* CE event flags */
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enum {
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NVGPU_CE_CONTEXT_JOB_COMPLETED = (1 << 0),
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NVGPU_CE_CONTEXT_JOB_TIMEDOUT = (1 << 1),
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NVGPU_CE_CONTEXT_SUSPEND = (1 << 2),
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NVGPU_CE_CONTEXT_RESUME = (1 << 3),
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};
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/* CE app state machine flags */
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enum {
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NVGPU_CE_ACTIVE = (1 << 0),
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NVGPU_CE_SUSPEND = (1 << 1),
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};
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/* gpu context state machine flags */
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enum {
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NVGPU_CE_GPU_CTX_ALLOCATED = (1 << 0),
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NVGPU_CE_GPU_CTX_DELETED = (1 << 1),
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};
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/* global ce app db */
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struct gk20a_ce_app {
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bool initialised;
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struct mutex app_mutex;
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int app_state;
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struct list_head allocated_contexts;
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u32 ctx_count;
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u32 next_ctx_id;
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};
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/* ce context db */
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struct gk20a_gpu_ctx {
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struct gk20a *g;
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struct device *dev;
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u32 ctx_id;
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struct mutex gpu_ctx_mutex;
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int gpu_ctx_state;
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ce_event_callback user_event_callback;
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/* channel related data */
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struct channel_gk20a *ch;
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struct vm_gk20a *vm;
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/* cmd buf mem_desc */
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struct mem_desc cmd_buf_mem;
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struct list_head list;
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u64 submitted_seq_number;
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u64 completed_seq_number;
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u32 cmd_buf_read_queue_offset;
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u32 cmd_buf_end_queue_offset;
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};
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/* global CE app related apis */
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int gk20a_init_ce_support(struct gk20a *g);
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void gk20a_ce_suspend(struct gk20a *g);
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void gk20a_ce_destroy(struct gk20a *g);
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/* CE app utility functions */
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u32 gk20a_ce_create_context_with_cb(struct device *dev,
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int runlist_id,
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int priority,
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int timeslice,
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int runlist_level,
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ce_event_callback user_event_callback);
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int gk20a_ce_execute_ops(struct device *dev,
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u32 ce_ctx_id,
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u64 src_buf,
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u64 dst_buf,
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u64 size,
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unsigned int payload,
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int launch_flags,
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int request_operation,
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struct gk20a_fence *gk20a_fence_in,
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u32 submit_flags,
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struct gk20a_fence **gk20a_fence_out);
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void gk20a_ce_delete_context(struct device *dev,
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u32 ce_ctx_id);
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#ifdef CONFIG_DEBUG_FS
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/* CE app debugfs api */
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void gk20a_ce_debugfs_init(struct device *dev);
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#endif
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#endif /*__CE2_GK20A_H__*/
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