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1c40d09c4c
bug 1648908 This commit adds support for FECS ctxsw tracing. Code is compiled conditionnaly under CONFIG_GK20_CTXSW_TRACE. This feature requires an updated FECS ucode that writes one record to a ring buffer on each context switch. On RM/Kernel side, the GPU driver reads records from the master ring buffer and generates trace entries into a user-facing VM ring buffer. For each record in the master ring buffer, RM/Kernel has to retrieve the vmid+pid of the user process that submitted related work. Features currently implemented: - master ring buffer allocation - debugfs to dump master ring buffer - FECS record per context switch (with both current and new contexts) - dedicated device for ctxsw tracing (access to VM ring buffer) - SOF generation (and access to PTIMER) - VM ring buffer allocation, and reconfiguration - enable/disable tracing at user level - event-based trace filtering - context_ptr to vmid+pid mapping - read system call for ctxsw dev - mmap system call for ctxsw dev (direct access to VM ring buffer) - poll system call for ctxsw dev - save/restore register on ELPG/CG6 - separate user ring from FECS ring handling Features requiring ucode changes: - enable/disable tracing at FECS level - actual busy time on engine (bug 1642354) - master ring buffer threshold interrupt (P1) - API for GPU to CPU timestamp conversion (P1) - vmid/pid/uid based filtering (P1) Change-Id: I8e39c648221ee0fa09d5df8524b03dca83fe24f3 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1022737 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
110 lines
3.3 KiB
C
110 lines
3.3 KiB
C
/*
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* Copyright (c) 2013-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Function naming determines intended use:
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*
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* <x>_r(void) : Returns the offset for register <x>.
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*
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* <x>_o(void) : Returns the offset for element <x>.
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*
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* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
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*
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* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
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*
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* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
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* and masked to place it at field <y> of register <x>. This value
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* can be |'d with others to produce a full register value for
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* register <x>.
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*
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* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
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* value can be ~'d and then &'d to clear the value of field <y> for
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* register <x>.
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*
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* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
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* to place it at field <y> of register <x>. This value can be |'d
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* with others to produce a full register value for <x>.
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*
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* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
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* <x> value 'r' after being shifted to place its LSB at bit 0.
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* This value is suitable for direct comparison with other unshifted
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* values appropriate for use in field <y> of register <x>.
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*
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* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
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* field <y> of register <x>. This value is suitable for direct
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_timer_gk20a_h_
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#define _hw_timer_gk20a_h_
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static inline u32 timer_pri_timeout_r(void)
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{
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return 0x00009080;
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}
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static inline u32 timer_pri_timeout_period_f(u32 v)
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{
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return (v & 0xffffff) << 0;
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}
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static inline u32 timer_pri_timeout_period_m(void)
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{
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return 0xffffff << 0;
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}
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static inline u32 timer_pri_timeout_period_v(u32 r)
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{
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return (r >> 0) & 0xffffff;
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}
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static inline u32 timer_pri_timeout_en_f(u32 v)
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{
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return (v & 0x1) << 31;
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}
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static inline u32 timer_pri_timeout_en_m(void)
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{
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return 0x1 << 31;
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}
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static inline u32 timer_pri_timeout_en_v(u32 r)
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{
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return (r >> 31) & 0x1;
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}
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static inline u32 timer_pri_timeout_en_en_enabled_f(void)
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{
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return 0x80000000;
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}
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static inline u32 timer_pri_timeout_en_en_disabled_f(void)
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{
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return 0x0;
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}
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static inline u32 timer_pri_timeout_save_0_r(void)
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{
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return 0x00009084;
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}
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static inline u32 timer_pri_timeout_save_1_r(void)
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{
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return 0x00009088;
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}
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static inline u32 timer_pri_timeout_fecs_errcode_r(void)
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{
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return 0x0000908c;
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}
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static inline u32 timer_time_0_r(void)
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{
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return 0x00009400;
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}
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static inline u32 timer_time_1_r(void)
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{
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return 0x00009410;
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}
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#endif
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