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415e427d41
Move chip specific fbpa files to hal/fbpa. Update Makefiles and include directives to make new locations. JIRA NVGPU-3257 Change-Id: Ifa4eebcd5ac8be620027400e75c199e4cf38bd80 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2107481 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
106 lines
3.6 KiB
C
106 lines
3.6 KiB
C
/*
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* TU104 FBPA
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*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/types.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/hw/tu104/hw_fbpa_tu104.h>
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#include "hal/fbpa/fbpa_tu104.h"
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int tu104_fbpa_init(struct gk20a *g)
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{
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u32 val;
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val = gk20a_readl(g, fbpa_ecc_intr_ctrl_r());
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val |= fbpa_ecc_intr_ctrl_sec_intr_en_enabled_f() |
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fbpa_ecc_intr_ctrl_ded_intr_en_enabled_f();
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gk20a_writel(g, fbpa_ecc_intr_ctrl_r(), val);
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/* read back broadcast register */
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(void) gk20a_readl(g, fbpa_ecc_intr_ctrl_r());
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return 0;
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}
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static void tu104_fbpa_handle_ecc_intr(struct gk20a *g,
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u32 fbpa_id, u32 subp_id)
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{
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u32 status, sec_cnt, ded_cnt;
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u32 offset = nvgpu_get_litter_value(g, GPU_LIT_FBPA_STRIDE) * fbpa_id;
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u32 cnt_idx = fbpa_id * 2U + subp_id;
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status = gk20a_readl(g, offset + fbpa_0_ecc_status_r(subp_id));
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if ((status & fbpa_0_ecc_status_sec_counter_overflow_pending_f()) != 0U) {
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nvgpu_err(g, "fbpa %u subp %u ecc sec counter overflow",
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fbpa_id, subp_id);
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}
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if ((status & fbpa_0_ecc_status_ded_counter_overflow_pending_f()) != 0U) {
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nvgpu_err(g, "fbpa %u subp %u ecc ded counter overflow",
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fbpa_id, subp_id);
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}
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if ((status & fbpa_0_ecc_status_sec_intr_pending_f()) != 0U) {
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sec_cnt = gk20a_readl(g,
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offset + fbpa_0_ecc_sec_count_r(subp_id));
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gk20a_writel(g, offset + fbpa_0_ecc_sec_count_r(subp_id), 0u);
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g->ecc.fbpa.fbpa_ecc_sec_err_count[cnt_idx].counter += sec_cnt;
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}
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if ((status & fbpa_0_ecc_status_ded_intr_pending_f()) != 0U) {
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ded_cnt = gk20a_readl(g,
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offset + fbpa_0_ecc_ded_count_r(subp_id));
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gk20a_writel(g, offset + fbpa_0_ecc_ded_count_r(subp_id), 0u);
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g->ecc.fbpa.fbpa_ecc_ded_err_count[cnt_idx].counter += ded_cnt;
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}
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gk20a_writel(g, offset + fbpa_0_ecc_status_r(subp_id), status);
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}
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void tu104_fbpa_handle_intr(struct gk20a *g, u32 fbpa_id)
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{
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u32 offset, status;
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u32 ecc_subp0_mask = fbpa_0_intr_status_sec_subp0_pending_f() |
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fbpa_0_intr_status_ded_subp0_pending_f();
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u32 ecc_subp1_mask = fbpa_0_intr_status_sec_subp1_pending_f() |
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fbpa_0_intr_status_ded_subp1_pending_f();
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offset = nvgpu_get_litter_value(g, GPU_LIT_FBPA_STRIDE) * fbpa_id;
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status = gk20a_readl(g, offset + fbpa_0_intr_status_r());
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if ((status & (ecc_subp0_mask | ecc_subp1_mask)) == 0U) {
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nvgpu_err(g, "unknown interrupt fbpa %u status %08x",
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fbpa_id, status);
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return;
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}
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if ((status & ecc_subp0_mask) != 0U) {
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tu104_fbpa_handle_ecc_intr(g, fbpa_id, 0u);
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}
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if ((status & ecc_subp1_mask) != 0U) {
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tu104_fbpa_handle_ecc_intr(g, fbpa_id, 1u);
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}
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}
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