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35e9663bd0
Moved init/deinit eng method buffers from fifo to tsg - tsg.init_eng_method_buffers - tsg.deinit_eng_method_buffers Moved gv11b_fifo_init_ramfc_eng_method_buffer to the following tsg HAL: - tsg.bind_channel_eng_method_buffers This HAL is now called during bind_channel. Added the following ramin HAL: - ramin.set_ramfc_eng_method_buffer Jira NVGPU-2979 Change-Id: I96f6ff15d2176d4e3714fa8fe65a9126b3fff82c Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2087185 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
122 lines
4.0 KiB
C
122 lines
4.0 KiB
C
/*
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* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
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#include "hal/fifo/ramin_gv11b.h"
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void gv11b_ramin_set_gr_ptr(struct gk20a *g,
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struct nvgpu_mem *inst_block, u64 gpu_va)
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{
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u32 addr_lo = u64_lo32(gpu_va) >> ram_in_base_shift_v();
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u32 addr_hi = u64_hi32(gpu_va);
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/* point this address to engine_wfi_ptr */
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nvgpu_mem_wr32(g, inst_block, ram_in_engine_wfi_target_w(),
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ram_in_engine_cs_wfi_v() |
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ram_in_engine_wfi_mode_f(ram_in_engine_wfi_mode_virtual_v()) |
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ram_in_engine_wfi_ptr_lo_f(addr_lo));
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nvgpu_mem_wr32(g, inst_block, ram_in_engine_wfi_ptr_hi_w(),
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ram_in_engine_wfi_ptr_hi_f(addr_hi));
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}
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static void gv11b_subctx_commit_valid_mask(struct gk20a *g,
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struct nvgpu_mem *inst_block)
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{
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u32 id;
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/* Make all subctx pdbs valid */
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for (id = 0U; id < ram_in_sc_pdb_valid__size_1_v(); id += 32U) {
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nvgpu_mem_wr32(g, inst_block, ram_in_sc_pdb_valid_w(id), U32_MAX);
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}
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}
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static void gv11b_subctx_commit_pdb(struct gk20a *g,
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struct nvgpu_mem *inst_block, struct nvgpu_mem *pdb_mem,
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bool replayable)
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{
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u32 lo, hi;
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u32 subctx_id = 0;
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u32 format_word;
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u32 pdb_addr_lo, pdb_addr_hi;
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u64 pdb_addr;
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u32 max_subctx_count = ram_in_sc_page_dir_base_target__size_1_v();
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u32 aperture = nvgpu_aperture_mask(g, pdb_mem,
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ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(),
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ram_in_sc_page_dir_base_target_sys_mem_coh_v(),
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ram_in_sc_page_dir_base_target_vid_mem_v());
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pdb_addr = nvgpu_mem_get_addr(g, pdb_mem);
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pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());
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pdb_addr_hi = u64_hi32(pdb_addr);
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format_word = ram_in_sc_page_dir_base_target_f(
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aperture, 0) |
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ram_in_sc_page_dir_base_vol_f(
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ram_in_sc_page_dir_base_vol_true_v(), 0) |
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ram_in_sc_use_ver2_pt_format_f(1, 0) |
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ram_in_sc_big_page_size_f(1, 0) |
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ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo);
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if (replayable) {
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format_word |=
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ram_in_sc_page_dir_base_fault_replay_tex_f(1, 0) |
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ram_in_sc_page_dir_base_fault_replay_gcc_f(1, 0);
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}
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nvgpu_log(g, gpu_dbg_info, " pdb info lo %x hi %x",
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format_word, pdb_addr_hi);
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for (subctx_id = 0U; subctx_id < max_subctx_count; subctx_id++) {
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lo = ram_in_sc_page_dir_base_vol_w(subctx_id);
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hi = ram_in_sc_page_dir_base_hi_w(subctx_id);
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nvgpu_mem_wr32(g, inst_block, lo, format_word);
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nvgpu_mem_wr32(g, inst_block, hi, pdb_addr_hi);
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}
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}
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void gv11b_ramin_init_subctx_pdb(struct gk20a *g,
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struct nvgpu_mem *inst_block, struct nvgpu_mem *pdb_mem,
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bool replayable)
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{
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gv11b_subctx_commit_pdb(g, inst_block, pdb_mem, replayable);
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gv11b_subctx_commit_valid_mask(g, inst_block);
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}
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void gv11b_ramin_set_eng_method_buffer(struct gk20a *g,
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struct nvgpu_mem *inst_block, u64 gpu_va)
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{
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u32 addr_lo = u64_lo32(gpu_va);
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u32 addr_hi = u64_hi32(gpu_va);
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nvgpu_mem_wr32(g, inst_block, ram_in_eng_method_buffer_addr_lo_w(),
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addr_lo);
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nvgpu_mem_wr32(g, inst_block, ram_in_eng_method_buffer_addr_hi_w(),
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addr_hi);
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}
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