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1a843ba051
Move nvgpu_gr_zbc_entry and nvgpu_gr_zbc to a priv header and add APIs to access members of those structs. JIRA NVGPU-3060 Change-Id: I1255f3ebda03f599aed3706136c0909491023067 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2091214 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
87 lines
2.9 KiB
C
87 lines
2.9 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gr/zbc.h>
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#include "zbc_gm20b.h"
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#include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
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int gm20b_gr_zbc_add_color(struct gk20a *g,
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struct nvgpu_gr_zbc_entry *color_val, u32 index)
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{
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/* update ds table */
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nvgpu_writel(g, gr_ds_zbc_color_r_r(),
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gr_ds_zbc_color_r_val_f(
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nvgpu_gr_zbc_get_entry_color_ds(color_val, 0)));
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nvgpu_writel(g, gr_ds_zbc_color_g_r(),
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gr_ds_zbc_color_g_val_f(
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nvgpu_gr_zbc_get_entry_color_ds(color_val, 1)));
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nvgpu_writel(g, gr_ds_zbc_color_b_r(),
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gr_ds_zbc_color_b_val_f(
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nvgpu_gr_zbc_get_entry_color_ds(color_val, 2)));
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nvgpu_writel(g, gr_ds_zbc_color_a_r(),
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gr_ds_zbc_color_a_val_f(
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nvgpu_gr_zbc_get_entry_color_ds(color_val, 3)));
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nvgpu_writel(g, gr_ds_zbc_color_fmt_r(),
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gr_ds_zbc_color_fmt_val_f(
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nvgpu_gr_zbc_get_entry_format(color_val)));
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nvgpu_writel(g, gr_ds_zbc_tbl_index_r(),
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gr_ds_zbc_tbl_index_val_f(index + NVGPU_GR_ZBC_STARTOF_TABLE));
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/* trigger the write */
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nvgpu_writel(g, gr_ds_zbc_tbl_ld_r(),
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gr_ds_zbc_tbl_ld_select_c_f() |
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gr_ds_zbc_tbl_ld_action_write_f() |
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gr_ds_zbc_tbl_ld_trigger_active_f());
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return 0;
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}
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int gm20b_gr_zbc_add_depth(struct gk20a *g,
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struct nvgpu_gr_zbc_entry *depth_val, u32 index)
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{
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/* update ds table */
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nvgpu_writel(g, gr_ds_zbc_z_r(),
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gr_ds_zbc_z_val_f(
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nvgpu_gr_zbc_get_entry_depth(depth_val)));
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nvgpu_writel(g, gr_ds_zbc_z_fmt_r(),
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gr_ds_zbc_z_fmt_val_f(
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nvgpu_gr_zbc_get_entry_format(depth_val)));
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nvgpu_writel(g, gr_ds_zbc_tbl_index_r(),
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gr_ds_zbc_tbl_index_val_f(index + NVGPU_GR_ZBC_STARTOF_TABLE));
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/* trigger the write */
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nvgpu_writel(g, gr_ds_zbc_tbl_ld_r(),
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gr_ds_zbc_tbl_ld_select_z_f() |
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gr_ds_zbc_tbl_ld_action_write_f() |
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gr_ds_zbc_tbl_ld_trigger_active_f());
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return 0;
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}
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