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a6f0ce7971
Move the code involved in dealing with minion into a separate unit called "nvlink_minion". This unit includes minion HW access, ucode handling, exposing state of minion and also dealing with minion interrupts. The interfaces to this unit are partially exposed using g->ops.nvlink.minion ops and rest are part of nvlink_minion.h public header. JIRA NVGPU-2860 Change-Id: Iea9288ea5f0b26688540b1eb8ab64afd756941a4 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2030103 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
64 lines
2.1 KiB
C
64 lines
2.1 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifdef CONFIG_TEGRA_NVLINK
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#include <nvgpu/nvlink_minion.h>
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#include "minion_gv100.h"
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#include "minion_tu104.h"
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#include <nvgpu/hw/tu104/hw_minion_tu104.h>
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struct gk20a;
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u32 tu104_nvlink_minion_get_dlcmd_ordinal(struct gk20a *g,
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enum nvgpu_nvlink_minion_dlcmd dlcmd)
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{
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u32 dlcmd_ordinal;
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switch (dlcmd) {
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case NVGPU_NVLINK_MINION_DLCMD_INITRXTERM:
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dlcmd_ordinal = 0x05U;
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break;
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case NVGPU_NVLINK_MINION_DLCMD_TURING_RXDET:
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dlcmd_ordinal = minion_nvlink_dl_cmd_command_turing_rxdet_v();
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break;
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case NVGPU_NVLINK_MINION_DLCMD_TXCLKSWITCH_PLL:
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dlcmd_ordinal = minion_nvlink_dl_cmd_command_txclkswitch_pll_v();
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break;
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case NVGPU_NVLINK_MINION_DLCMD_TURING_INITDLPL_TO_CHIPA:
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dlcmd_ordinal = minion_nvlink_dl_cmd_command_turing_initdlpl_to_chipa_v();
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break;
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case NVGPU_NVLINK_MINION_DLCMD_INITTL:
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dlcmd_ordinal = minion_nvlink_dl_cmd_command_inittl_v();
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break;
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default:
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dlcmd_ordinal = gv100_nvlink_minion_get_dlcmd_ordinal(g, dlcmd);
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break;
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}
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return dlcmd_ordinal;
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}
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#endif /* CONFIG_TEGRA_NVLINK */
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